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/freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mmsys.yaml4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
7 title: MediaTek mmsys controller
13 The MediaTek mmsys system controller provides clock control, routing control,
14 and miscellaneous control in mmsys partition.
24 - mediatek,mt2701-mmsys
25 - mediatek,mt2712-mmsys
26 - mediatek,mt6765-mmsys
27 - mediatek,mt6779-mmsys
28 - mediatek,mt6795-mmsys
29 - mediatek,mt6797-mmsys
[all...]
H A Dmediatek,mmsys.txt1 Mediatek mmsys controller
4 The Mediatek mmsys system controller provides clock control, routing control,
5 and miscellaneous control in mmsys partition.
10 - "mediatek,mt2701-mmsys", "syscon"
11 - "mediatek,mt2712-mmsys", "syscon"
12 - "mediatek,mt6765-mmsys", "syscon"
13 - "mediatek,mt6779-mmsys", "syscon"
14 - "mediatek,mt6797-mmsys", "syscon"
15 - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
16 - "mediatek,mt8167-mmsys", "syscon"
[all …]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623n.dtsi51 mmsys: syscon@14000000 { label
52 compatible = "mediatek,mt7623-mmsys",
53 "mediatek,mt2701-mmsys",
65 clocks = <&mmsys CLK_MM_SMI_LARB0>,
66 <&mmsys CLK_MM_SMI_LARB0>;
133 <&mmsys CLK_MM_SMI_COMMON>,
144 clocks = <&mmsys CLK_MM_DISP_OVL>;
153 clocks = <&mmsys CLK_MM_DISP_RDMA>;
162 clocks = <&mmsys CLK_MM_DISP_WDMA>;
171 clocks = <&mmsys CLK_MM_MDP_BLS_26
[all...]
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt5 MMSYS register space. The connections between them can be configured by output
12 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
80 mmsys: clock-controller@14000000 {
81 compatible = "mediatek,mt8173-mmsys", "syscon";
92 clocks = <&mmsys CLK_MM_DISP_OVL0>;
102 clocks = <&mmsys CLK_MM_DISP_OVL1>;
112 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
123 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
133 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
143 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
[all …]
H A Dmediatek,hdmi.txt20 MMSYS_CONFIG region: <&mmsys 0x900>.
91 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
92 <&mmsys CLK_MM_HDMI_PLLCK>,
93 <&mmsys CLK_MM_HDMI_AUDIO>,
94 <&mmsys CLK_MM_HDMI_SPDIF>;
100 mediatek,syscon-hdmi = <&mmsys 0x900>;
H A Dmediatek,hdmi.yaml103 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
104 <&mmsys CLK_MM_HDMI_PLLCK>,
105 <&mmsys CLK_MM_HDMI_AUDIO>,
106 <&mmsys CLK_MM_HDMI_SPDIF>;
112 mediatek,syscon-hdmi = <&mmsys 0x900>;
H A Dmediatek,dsi.txt50 clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
53 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
H A Dmediatek,dsi.yaml111 clocks = <&mmsys CLK_MM_DSI0_MM>,
112 <&mmsys CLK_MM_DSI0_IF>,
115 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
H A Dmediatek,dpi.txt29 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
30 <&mmsys CLK_MM_DPI_ENGINE>,
H A Dmediatek,od.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
59 clocks = <&mmsys CLK_MM_DISP_OD>;
H A Dmediatek,ufoe.yaml19 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
69 clocks = <&mmsys CLK_MM_DISP_UFOE>;
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmediatek-mdp.txt36 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
37 <&mmsys CLK_MM_MUTEX_32K>;
46 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
47 <&mmsys CLK_MM_MUTEX_32K>;
55 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
62 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
69 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
76 clocks = <&mmsys CLK_MM_MDP_WDMA>;
84 clocks = <&mmsys CLK_MM_MDP_WROT0>;
92 clocks = <&mmsys CLK_MM_MDP_WROT1>;
H A Dmediatek,mdp3-rdma.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
162 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
163 <&mmsys CLK_MM_MDP_RSZ1>;
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8173.dtsi996 mmsys: syscon@14000000 { label
997 compatible = "mediatek,mt8173-mmsys", "syscon";
1013 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1014 <&mmsys CLK_MM_MUTEX_32K>;
1023 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1024 <&mmsys CLK_MM_MUTEX_32K>;
1032 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1039 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1046 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1053 clocks = <&mmsys CLK_MM_MDP_WDMA>;
[all …]
H A Dmt8183.dtsi906 <&mmsys CLK_MM_SMI_COMMON>,
907 <&mmsys CLK_MM_SMI_LARB0>,
908 <&mmsys CLK_MM_SMI_LARB1>,
909 <&mmsys CLK_MM_GALS_COMM0>,
910 <&mmsys CLK_MM_GALS_COMM1>,
911 <&mmsys CLK_MM_GALS_CCU2MM>,
912 <&mmsys CLK_MM_GALS_IPU12MM>,
913 <&mmsys CLK_MM_GALS_IMG2MM>,
914 <&mmsys CLK_MM_GALS_CAM2MM>,
915 <&mmsys CLK_MM_GALS_IPU2MM>;
[all …]
H A Dmt8167.dtsi127 mmsys: syscon@14000000 { label
128 compatible = "mediatek,mt8167-mmsys", "syscon";
136 clocks = <&mmsys CLK_MM_SMI_COMMON>,
137 <&mmsys CLK_MM_SMI_COMMON>;
146 clocks = <&mmsys CLK_MM_SMI_LARB0>,
147 <&mmsys CLK_MM_SMI_LARB0>;
H A Dmt8365.dtsi319 <&mmsys CLK_MM_MM_SMI_COMMON>,
320 <&mmsys CLK_MM_MM_SMI_COMM0>,
321 <&mmsys CLK_MM_MM_SMI_COMM1>,
322 <&mmsys CLK_MM_MM_SMI_LARB0>;
730 mmsys: syscon@14000000 { label
731 compatible = "mediatek,mt8365-mmsys", "syscon";
739 clocks = <&mmsys CLK_MM_MM_SMI_COMMON>,
740 <&mmsys CLK_MM_MM_SMI_COMMON>,
741 <&mmsys CLK_MM_MM_SMI_COMM0>,
742 <&mmsys CLK_MM_MM_SMI_COMM1>;
[all …]
H A Dmt8192.dtsi573 <&mmsys CLK_MM_SMI_INFRA>,
574 <&mmsys CLK_MM_SMI_COMMON>,
575 <&mmsys CLK_MM_SMI_GALS>,
576 <&mmsys CLK_MM_SMI_IOMMU>;
1452 mmsys: syscon@14000000 { label
1453 compatible = "mediatek,mt8192-mmsys", "syscon";
1466 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1476 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1477 <&mmsys CLK_MM_SMI_INFRA>,
1478 <&mmsys CLK_MM_SMI_GALS>,
[all …]
H A Dmt8186.dtsi984 <&mmsys CLK_MM_SMI_INFRA>,
985 <&mmsys CLK_MM_SMI_COMMON>,
986 <&mmsys CLK_MM_SMI_GALS>,
987 <&mmsys CLK_MM_SMI_IOMMU>;
1763 mmsys: syscon@14000000 { label
1764 compatible = "mediatek,mt8186-mmsys", "syscon";
1776 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1787 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1788 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1796 clocks = <&mmsys CLK_MM_SMI_COMMON>,
[all …]
H A Dmt2712e.dtsi994 mmsys: syscon@14000000 { label
995 compatible = "mediatek,mt2712-mmsys", "syscon";
1006 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1007 <&mmsys CLK_MM_SMI_LARB0>;
1015 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1016 <&mmsys CLK_MM_SMI_COMMON>;
1026 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1027 <&mmsys CLK_MM_SMI_LARB4>;
1037 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1038 <&mmsys CLK_MM_SMI_LARB5>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-mtk-disp.txt16 - "mm": sync signals from the modules of mmsys.
27 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
28 <&mmsys CLK_MM_DISP_PWM0MM>;
H A Dmediatek,pwm-disp.yaml77 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
78 <&mmsys CLK_MM_DISP_PWM0MM>;
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dmtk-gce.txt62 mmsys: clock-controller@14000000 {
63 compatible = "mediatek,mt8173-mmsys";
79 clocks = <&mmsys CLK_MM_MUTEX_32K>;
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmediatek,smi-larb.txt46 clocks = <&mmsys CLK_MM_SMI_LARB0>,
47 <&mmsys CLK_MM_SMI_LARB0>;
H A Dmediatek,smi-common.txt47 clocks = <&mmsys CLK_MM_SMI_COMMON>,
48 <&mmsys CLK_MM_SMI_COMMON>;

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