| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_mmio.c | 28 * On multi-tile devices, partition the BAR space for MMIO on each tile,
39 * | tile1->mmio.regs |
43 * | tile0->mmio.regs |
52 xe_mmio_init(&tile->mmio, tile, xe->mmio.regs + id * tile_mmio_size, SZ_4M); in mmio_multi_tile_setup()
56 * xe_mmio_probe_tiles() - Initialize all tiles' MMIO
59 * Initialize the remaining tiles' MMIO instances.
74 if (xe->mmio.size < xe->info.tile_count * tile_mmio_size) { in xe_mmio_probe_tiles()
76 xe->info.tile_count, xe->mmio.size); in xe_mmio_probe_tiles()
88 xe->mmio in mmio_fini()
134 xe_mmio_init(struct xe_mmio * mmio,struct xe_tile * tile,void __iomem * ptr,u32 size) xe_mmio_init() argument
143 mmio_available(struct xe_mmio * mmio) mmio_available() argument
148 mmio_flush_pending_writes(struct xe_mmio * mmio) mmio_flush_pending_writes() argument
161 xe_mmio_read8(struct xe_mmio * mmio,struct xe_reg reg) xe_mmio_read8() argument
177 xe_mmio_write8(struct xe_mmio * mmio,struct xe_reg reg,u8 val) xe_mmio_write8() argument
189 xe_mmio_read16(struct xe_mmio * mmio,struct xe_reg reg) xe_mmio_read16() argument
205 xe_mmio_write32(struct xe_mmio * mmio,struct xe_reg reg,u32 val) xe_mmio_write32() argument
221 xe_mmio_read32(struct xe_mmio * mmio,struct xe_reg reg) xe_mmio_read32() argument
242 xe_mmio_rmw32(struct xe_mmio * mmio,struct xe_reg reg,u32 clr,u32 set) xe_mmio_rmw32() argument
253 xe_mmio_write32_and_verify(struct xe_mmio * mmio,struct xe_reg reg,u32 val,u32 mask,u32 eval) xe_mmio_write32_and_verify() argument
264 xe_mmio_in_range(const struct xe_mmio * mmio,const struct xe_mmio_range * range,struct xe_reg reg) xe_mmio_in_range() argument
295 xe_mmio_read64_2x32(struct xe_mmio * mmio,struct xe_reg reg) xe_mmio_read64_2x32() argument
324 __xe_mmio_wait32(struct xe_mmio * mmio,struct xe_reg reg,u32 mask,u32 val,u32 timeout_us,u32 * out_val,bool atomic,bool expect_match) __xe_mmio_wait32() argument
396 xe_mmio_wait32(struct xe_mmio * mmio,struct xe_reg reg,u32 mask,u32 val,u32 timeout_us,u32 * out_val,bool atomic) xe_mmio_wait32() argument
415 xe_mmio_wait32_not(struct xe_mmio * mmio,struct xe_reg reg,u32 mask,u32 val,u32 timeout_us,u32 * out_val,bool atomic) xe_mmio_wait32_not() argument
433 xe_mmio_init_vf_view(struct xe_mmio * mmio,const struct xe_mmio * base,unsigned int vfid) xe_mmio_init_vf_view() argument
[all...] |
| H A D | xe_i2c.c | 42 * I2C) if the registers of that controller are mapped to the MMIO, and also the
58 static inline void xe_i2c_read_endpoint(struct xe_mmio *mmio, void *ep) in xe_i2c_read_endpoint() argument
62 val[0] = xe_mmio_read32(mmio, REG_SG_REMAP_ADDR_PREFIX); in xe_i2c_read_endpoint()
63 val[1] = xe_mmio_read32(mmio, REG_SG_REMAP_ADDR_POSTFIX); in xe_i2c_read_endpoint()
70 stat = xe_mmio_read32(i2c->mmio, I2C_REG(DW_IC_SMBUS_INTR_STAT)); in xe_i2c_handle_smbus_alert()
74 xe_mmio_write32(i2c->mmio, I2C_REG(DW_IC_CLR_SMBUS_INTR), stat); in xe_i2c_handle_smbus_alert()
79 xe_mmio_rmw32(i2c->mmio, I2C_CONFIG_CMD, PCI_COMMAND_INTX_DISABLE, 0); in xe_i2c_handle_smbus_alert()
193 struct xe_mmio *mmio = xe_root_tile_mmio(xe); in xe_i2c_irq_reset() local
198 xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_INTX_DISABLE); in xe_i2c_irq_reset()
199 xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, ACPI_INTR_EN, 0); in xe_i2c_irq_reset()
[all …]
|
| /linux/sound/pci/au88x0/ |
| H A D | au88x0_xtalk.c | 248 hwwrite(vortex->mmio, 0x24200 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetLeftEQ()
249 hwwrite(vortex->mmio, 0x24204 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetLeftEQ()
250 hwwrite(vortex->mmio, 0x24208 + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetLeftEQ()
251 hwwrite(vortex->mmio, 0x2420c + i * 0x24, coefs[i][3]); in vortex_XtalkHw_SetLeftEQ()
252 hwwrite(vortex->mmio, 0x24210 + i * 0x24, coefs[i][4]); in vortex_XtalkHw_SetLeftEQ()
254 hwwrite(vortex->mmio, 0x24538, arg_0 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
255 hwwrite(vortex->mmio, 0x2453C, arg_4 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
265 hwwrite(vortex->mmio, 0x242b4 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetRightEQ()
266 hwwrite(vortex->mmio, 0x242b8 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetRightEQ()
267 hwwrite(vortex->mmio, 0x242bc + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetRightEQ()
[all …]
|
| H A D | au88x0_core.c | 79 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_en_sr()
80 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); in vortex_mixer_en_sr()
84 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_dis_sr()
85 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); in vortex_mixer_dis_sr()
93 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
95 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
102 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
114 a = hwread(vortex->mmio,
139 a = hwread(vortex->mmio,
143 hwwrite(vortex->mmio,
[all …]
|
| H A D | au88x0_eq.c | 41 hwwrite(vortex->mmio, 0x2b3c4, gain); in vortex_EqHw_SetTimeConsts()
42 hwwrite(vortex->mmio, 0x2b3c8, level); in vortex_EqHw_SetTimeConsts()
60 hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]); in vortex_EqHw_SetLeftCoefs()
61 hwwrite(vortex->mmio, 0x2b004 + n * 0x30, coefs[i + 1]); in vortex_EqHw_SetLeftCoefs()
64 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2]); in vortex_EqHw_SetLeftCoefs()
65 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3]); in vortex_EqHw_SetLeftCoefs()
66 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, coefs[i + 4]); in vortex_EqHw_SetLeftCoefs()
68 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, sign_invert(coefs[2 + i])); in vortex_EqHw_SetLeftCoefs()
69 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, sign_invert(coefs[3 + i])); in vortex_EqHw_SetLeftCoefs()
70 hwwrite(vortex->mmio, in vortex_EqHw_SetLeftCoefs()
[all...] |
| H A D | au88x0_synth.c | 32 //temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2)); in vortex_wt_setstereo()
33 temp = hwread(vortex->mmio, WT_STEREO(wt)); in vortex_wt_setstereo()
35 //hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp); in vortex_wt_setstereo()
36 hwwrite(vortex->mmio, WT_STEREO(wt), temp); in vortex_wt_setstereo()
45 temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0)); in vortex_wt_setdsout()
50 hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp); in vortex_wt_setdsout()
70 hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000); in vortex_wt_allocroute()
71 //hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff); in vortex_wt_allocroute()
73 hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000); in vortex_wt_allocroute()
74 //hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff); in vortex_wt_allocroute()
[all …]
|
| H A D | au88x0_mpu401.c | 16 /* Check for mpu401 mmio support. */
42 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) | in snd_vortex_midi()
44 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
48 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) & in snd_vortex_midi()
50 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
54 temp = hwread(vortex->mmio, VORTEX_CTRL2) & 0xffff00cf; in snd_vortex_midi()
56 hwwrite(vortex->mmio, VORTEX_CTRL2, temp); in snd_vortex_midi()
57 hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET); in snd_vortex_midi()
60 temp = hwread(vortex->mmio, VORTEX_MIDI_DATA); in snd_vortex_midi()
66 hwwrite(vortex->mmio, VORTEX_IRQ_CTR in snd_vortex_midi()
[all...] |
| H A D | au88x0_a3d.c | 25 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
27 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
29 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
31 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
51 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
54 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
57 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
66 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
69 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
72 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
[all …]
|
| /linux/drivers/video/fbdev/i810/ |
| H A D | i810_main.c | 162 * @mmio: address of register space
168 static void i810_screen_off(u8 __iomem *mmio, u8 mode) in i810_screen_off() argument
173 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
174 val = i810_readb(SR_DATA, mmio); in i810_screen_off()
178 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); in i810_screen_off()
179 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
180 i810_writeb(SR_DATA, mmio, val); in i810_screen_off()
185 * @mmio: address of register space
192 static void i810_dram_off(u8 __iomem *mmio, u8 mode) in i810_dram_off() argument
196 val = i810_readb(DRAMCH, mmio); in i810_dram_off()
211 i810_protect_regs(u8 __iomem * mmio,int mode) i810_protect_regs() argument
234 u8 __iomem *mmio = par->mmio_start_virtual; i810_load_pll() local
259 u8 __iomem *mmio = par->mmio_start_virtual; i810_load_vga() local
302 u8 __iomem *mmio = par->mmio_start_virtual; i810_load_vgax() local
329 u8 __iomem *mmio = par->mmio_start_virtual; i810_load_2d() local
349 i810_hires(u8 __iomem * mmio) i810_hires() argument
372 u8 __iomem *mmio = par->mmio_start_virtual; i810_load_pitch() local
402 u8 __iomem *mmio = par->mmio_start_virtual; i810_load_color() local
424 u8 __iomem *mmio = par->mmio_start_virtual; i810_load_regs() local
442 i810_write_dac(u8 regno,u8 red,u8 green,u8 blue,u8 __iomem * mmio) i810_write_dac() argument
451 i810_read_dac(u8 regno,u8 * red,u8 * green,u8 * blue,u8 __iomem * mmio) i810_read_dac() argument
465 u8 __iomem *mmio = par->mmio_start_virtual; i810_restore_pll() local
485 u8 __iomem *mmio = par->mmio_start_virtual; i810_restore_dac() local
497 u8 __iomem *mmio = par->mmio_start_virtual; i810_restore_vgax() local
531 u8 __iomem *mmio = par->mmio_start_virtual; i810_restore_vga() local
546 u8 __iomem *mmio = par->mmio_start_virtual; i810_restore_addr_map() local
560 u8 __iomem *mmio = par->mmio_start_virtual; i810_restore_2d() local
589 u8 __iomem *mmio = par->mmio_start_virtual; i810_restore_vga_state() local
612 u8 __iomem *mmio = par->mmio_start_virtual; i810_save_vgax() local
636 u8 __iomem *mmio = par->mmio_start_virtual; i810_save_vga() local
650 u8 __iomem *mmio = par->mmio_start_virtual; i810_save_2d() local
773 i810_enable_cursor(u8 __iomem * mmio,int mode) i810_enable_cursor() argument
823 u8 __iomem *mmio = par->mmio_start_virtual; i810_load_cursor_colors() local
853 u8 __iomem *mmio = par->mmio_start_virtual; i810_init_cursor() local
1204 u8 __iomem *mmio = par->mmio_start_virtual; i810fb_getcolreg() local
1287 u8 __iomem *mmio = par->mmio_start_virtual; i810fb_setcolreg() local
1393 u8 __iomem *mmio = par->mmio_start_virtual; i810fb_blank() local
1482 u8 __iomem *mmio = par->mmio_start_virtual; i810fb_cursor() local
1821 u8 __iomem *mmio = par->mmio_start_virtual; i810_init_device() local
[all...] |
| H A D | i810-i2c.c | 46 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setscl() local
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
59 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setsda() local
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
72 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getscl() local
74 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK); in i810i2c_getscl()
[all …]
|
| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-ufs.c | 40 void __iomem *mmio; member
61 void __iomem *mmio = phy->mmio; in ufs_mtk_phy_set_active() local
64 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); in ufs_mtk_phy_set_active()
65 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); in ufs_mtk_phy_set_active()
68 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_active()
69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_active()
72 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_active()
73 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_active()
76 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_active()
77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_active()
[all …]
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| /linux/drivers/net/ethernet/amd/ |
| H A D | amd8111e.c | 101 void __iomem *mmio = lp->mmio; in amd8111e_read_phy() local
105 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
107 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
110 ((reg & 0x1f) << 16), mmio + PHY_ACCESS); in amd8111e_read_phy()
112 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
131 void __iomem *mmio = lp->mmio; in amd8111e_write_phy() local
134 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
136 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
139 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); in amd8111e_write_phy()
142 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
[all …]
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| /linux/drivers/net/ethernet/intel/idpf/ |
| H A D | idpf_vf_dev.c | 12 * @mmio: struct that contains MMIO region info
15 static void idpf_vf_ctlq_reg_init(struct libie_mmio_info *mmio, in idpf_vf_ctlq_reg_init() argument
21 tx_reg->head = libie_pci_get_mmio_addr(mmio, VF_ATQH); in idpf_vf_ctlq_reg_init()
22 tx_reg->tail = libie_pci_get_mmio_addr(mmio, VF_ATQT); in idpf_vf_ctlq_reg_init()
23 tx_reg->len = libie_pci_get_mmio_addr(mmio, VF_ATQLEN); in idpf_vf_ctlq_reg_init()
24 tx_reg->addr_high = libie_pci_get_mmio_addr(mmio, VF_ATQBAH); in idpf_vf_ctlq_reg_init()
25 tx_reg->addr_low = libie_pci_get_mmio_addr(mmio, VF_ATQBAL); in idpf_vf_ctlq_reg_init()
30 rx_reg->head = libie_pci_get_mmio_addr(mmio, VF_ARQH); in idpf_vf_ctlq_reg_init()
31 rx_reg->tail = libie_pci_get_mmio_addr(mmio, VF_ARQT); in idpf_vf_ctlq_reg_init()
32 rx_reg->len = libie_pci_get_mmio_addr(mmio, VF_ARQLEN); in idpf_vf_ctlq_reg_init()
[all …]
|
| H A D | idpf_dev.c | 13 * @mmio: struct that contains MMIO region info
16 static void idpf_ctlq_reg_init(struct libie_mmio_info *mmio, in idpf_ctlq_reg_init() argument
22 tx_reg->head = libie_pci_get_mmio_addr(mmio, PF_FW_ATQH); in idpf_ctlq_reg_init()
23 tx_reg->tail = libie_pci_get_mmio_addr(mmio, PF_FW_ATQT); in idpf_ctlq_reg_init()
24 tx_reg->len = libie_pci_get_mmio_addr(mmio, PF_FW_ATQLEN); in idpf_ctlq_reg_init()
25 tx_reg->addr_high = libie_pci_get_mmio_addr(mmio, PF_FW_ATQBAH); in idpf_ctlq_reg_init()
26 tx_reg->addr_low = libie_pci_get_mmio_addr(mmio, PF_FW_ATQBAL); in idpf_ctlq_reg_init()
31 rx_reg->head = libie_pci_get_mmio_addr(mmio, PF_FW_ARQH); in idpf_ctlq_reg_init()
32 rx_reg->tail = libie_pci_get_mmio_addr(mmio, PF_FW_ARQT); in idpf_ctlq_reg_init()
33 rx_reg->len = libie_pci_get_mmio_addr(mmio, PF_FW_ARQLEN); in idpf_ctlq_reg_init()
[all …]
|
| /linux/sound/soc/au1x/ |
| H A D | psc.h | 13 void __iomem *mmio; member
26 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
27 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
28 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
29 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
30 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
31 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
32 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
33 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
34 #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
[all …]
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| /linux/drivers/net/wireless/mediatek/mt76/ |
| H A D | mmio.c | 14 val = readl(dev->mmio.regs + offset); in mt76_mmio_rr()
23 writel(val, dev->mmio.regs + offset); in mt76_mmio_wr()
40 dev->mmio.regs + offset + i); in mt76_mmio_write_copy()
46 writel(get_unaligned_le32(tmp), dev->mmio.regs + offset + i); in mt76_mmio_write_copy()
56 put_unaligned_le32(readl(dev->mmio.regs + offset + i), in mt76_mmio_read_copy()
62 put_unaligned_le32(readl(dev->mmio.regs + offset + i), tmp); in mt76_mmio_read_copy()
96 spin_lock_irqsave(&dev->mmio.irq_lock, flags); in mt76_set_irq_mask()
97 dev->mmio.irqmask &= ~clear; in mt76_set_irq_mask()
98 dev->mmio.irqmask |= set; in mt76_set_irq_mask()
100 if (mtk_wed_device_active(&dev->mmio.wed)) in mt76_set_irq_mask()
[all …]
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| /linux/drivers/net/wwan/iosm/ |
| H A D | iosm_ipc_mmio.h | 52 /* mmio scratchpad info */
68 * struct iosm_mmio - MMIO region mapped to the doorbell scratchpad.
69 * @base: Base address of MMIO region
94 * ipc_mmio_init - Allocate mmio instance data
95 * @mmio_addr: Mapped AP base address of the MMIO area.
98 * Returns: address of mmio instance data or NULL if fails.
106 * @ipc_mmio: Pointer to mmio instance
115 * MMIO instance to share it with CP during
117 * @ipc_mmio: Pointer to mmio instance
125 * @ipc_mmio: Pointer to mmio instance
[all …]
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| /linux/sound/soc/xilinx/ |
| H A D | xlnx_formatter_pcm.c | 77 void __iomem *mmio;
89 * @mmio: base address offset
96 void __iomem *mmio;
283 reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS; in xlnx_mm2s_irq_handler()
301 reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS; in xlnx_s2mm_irq_handler()
349 stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET; in xlnx_formatter_pcm_open()
358 stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET; in xlnx_formatter_pcm_open()
362 val = readl(adata->mmio in xlnx_formatter_pcm_open()
79 void __iomem *mmio; global() member
99 void __iomem *mmio; global() member
[all...] |
| /linux/tools/testing/selftests/kvm/ |
| H A D | coalesced_io_test.c | 19 u64 *mmio; member
53 WRITE_ONCE(*io->mmio, io->mmio_gpa + i); in guest_code()
60 WRITE_ONCE(*io->mmio, io->mmio_gpa + i); in guest_code()
64 WRITE_ONCE(*io->mmio, io->mmio_gpa + i); in guest_code()
88 * data_offset is garbage, e.g. an MMIO gpa. in vcpu_run_and_verify_io_exit()
95 TEST_ASSERT((!want_pio && (run->exit_reason == KVM_EXIT_MMIO && run->mmio.is_write && in vcpu_run_and_verify_io_exit()
96 run->mmio.phys_addr == io->mmio_gpa && run->mmio.len == 8 && in vcpu_run_and_verify_io_exit()
97 *(u64 *)run->mmio.data == io->mmio_gpa + io->ring_size - 1)) || in vcpu_run_and_verify_io_exit()
102 "(MMIO addr = 0x%llx, write = %u, len = %u, data = %lx)\n " in vcpu_run_and_verify_io_exit()
104 ring_start, want_pio ? 4 : 8, want_pio ? "PIO" : "MMIO", in vcpu_run_and_verify_io_exit()
[all …]
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| /linux/rust/kernel/ |
| H A D | io.rs | 178 /// Raw representation of an MMIO region.
183 /// the represented MMIO region does exist or is properly mapped. in offset_valid()
185 /// Instead, the bus specific MMIO implementation must convert this raw representation into an in offset_valid()
186 /// `Mmio` instance providing the actual memory accessors. Only by the conversion into an `Mmio` in offset_valid()
231 /// Returns the base address of the MMIO region.
237 /// Returns the size of the MMIO region.
311 /// backends (e.g. MMIO, PCI config space, etc.). in copy_read()
314 /// on which [`IoCapable<T>`] traits are implemented for the type. For example, for MMIO regions, in copy_read()
349 /// and `IoCapable<u32>`, but not `IoCapable<u64>`, while an MMIO regio
1121 pub struct Mmio<'a, T: ?Sized> { global() struct
1126 impl<T: ?Sized> Copy for Mmio<'_, T> {} global() implementation
1127 impl<T: ?Sized> Clone for Mmio<'_, T> { global() implementation
1134 impl<'a, T: ?Sized> Mmio<'a, T> { global() implementation
1151 unsafe impl<T: ?Sized + Sync> Send for Mmio<'_, T> {} global() implementation
1154 unsafe impl<T: ?Sized + Sync> Sync for Mmio<'_, T> {} global() implementation
1156 impl<'a, T: ?Sized + KnownSize> IoBase<'a> for Mmio<'a, T> { global() implementation
1289 impl<'a, T: ?Sized> Mmio<'a, T> { global() implementation
[all...] |
| /linux/drivers/ntb/hw/amd/ |
| H A D | ntb_hw_amd.c | 125 void __iomem *mmio, *peer_mmio; in amd_ntb_mw_set_trans() local
142 mmio = ndev->self_mmio; in amd_ntb_mw_set_trans()
166 write64(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
189 writel(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
355 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_enable() local
359 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_enable()
371 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_disable() local
375 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_disable()
432 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_read() local
434 return (u64)readw(mmio + AMD_DBSTAT_OFFSET); in amd_ntb_db_read()
[all …]
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-naneng-combphy.c | 207 void __iomem *mmio;
226 temp = readl(priv->mmio + reg);
228 writel(temp, priv->mmio + reg); in rockchip_combphy_param_write()
422 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
423 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
424 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
490 val = readl(priv->mmio + RK3568_PHYREG8); in rk_combphy_common_cfg_ssc()
492 writel(val, priv->mmio + RK3568_PHYREG8); in rk_combphy_common_cfg_ssc()
500 val = readl(priv->mmio + RK3568_PHYREG33); in rk_combphy_common_cfg_ssc()
502 writel(val, priv->mmio in rk_combphy_common_cfg_ssc()
203 void __iomem *mmio; global() member
[all...] |
| /linux/drivers/ntb/hw/intel/ |
| H A D | ntb_hw_gen1.c | 203 void __iomem *mmio) in ndev_db_read() argument
208 return ndev->reg->db_ioread(mmio); in ndev_db_read()
212 void __iomem *mmio) in ndev_db_write() argument
220 ndev->reg->db_iowrite(db_bits, mmio); in ndev_db_write()
226 void __iomem *mmio) in ndev_db_set_mask() argument
239 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_set_mask()
247 void __iomem *mmio) in ndev_db_clear_mask() argument
260 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_clear_mask()
297 void __iomem *mmio) in ndev_spad_read() argument
305 return ioread32(mmio + (idx << 2)); in ndev_spad_read()
[all …]
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| H A D | ntb_hw_gen3.c | 147 void __iomem *mmio; in gen3_setup_b2b_mw() local
151 mmio = ndev->self_mmio; in gen3_setup_b2b_mw()
155 iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
156 bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
160 iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
161 bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
165 iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET); in gen3_setup_b2b_mw()
166 iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET); in gen3_setup_b2b_mw()
262 void __iomem *mmio; in ndev_ntb3_debugfs_read() local
269 mmio = ndev->self_mmio; in ndev_ntb3_debugfs_read()
[all …]
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| /linux/drivers/net/ethernet/intel/libie/ |
| H A D | pci.c | 7 * libie_find_mmio_region - find MMIO region containing a range
8 * @mmio_list: list that contains MMIO region info
13 * MMIO regions mappings are traversed from oldest to newest.
15 * Return: pointer to a MMIO region overlapping with the range in any way or
40 * __libie_pci_get_mmio_addr - get the MMIO virtual address
41 * @mmio_info: contains list of MMIO regions
47 * through the non-linear MMIO regions that are mapped by the driver.
52 * Return: valid MMIO virtual address or NULL.
76 WARN_ONCE(true, "Access to an unmapped MMIO region (BAR%d, offset %pa)", in __libie_pci_get_mmio_addr()
84 * __libie_pci_map_mmio_region - map PCI device MMIO region
[all …]
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