/linux/drivers/gpu/host1x/ |
H A D | mipi.c | 131 struct tegra_mipi *mipi; member 136 static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi, in tegra_mipi_readl() argument 139 return readl(mipi->regs + (offset << 2)); in tegra_mipi_readl() 142 static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value, in tegra_mipi_writel() argument 145 writel(value, mipi->regs + (offset << 2)); in tegra_mipi_writel() 148 static int tegra_mipi_power_up(struct tegra_mipi *mipi) in tegra_mipi_power_up() argument 153 err = clk_enable(mipi->clk); in tegra_mipi_power_up() 157 value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up() 160 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_up() 163 tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up() [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | samsung,mipi-video-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/samsung,mipi-video-phy.yaml# 7 title: Samsung S5P/Exynos SoC MIPI CSIS/DSIM DPHY 15 For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the 17 0 - MIPI CSIS 0, 18 1 - MIPI DSIM 0, 19 2 - MIPI CSIS 1, 20 3 - MIPI DSIM 1. 22 samsung,exynos5420-mipi-video-phy and samsung,exynos5433-mipi-video-phy 24 4 - MIPI CSIS 2. 29 - samsung,s5pv210-mipi-video-phy [all …]
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H A D | mediatek,dsi-phy.yaml | 8 title: MediaTek MIPI Display Serial Interface (DSI) PHY 15 description: The MIPI DSI PHY supports up to 4-lane output. 25 - mediatek,mt7623-mipi-tx 26 - const: mediatek,mt2701-mipi-tx 29 - mediatek,mt6795-mipi-tx 30 - const: mediatek,mt8173-mipi-tx 33 - mediatek,mt8188-mipi-tx 34 - mediatek,mt8195-mipi-tx 35 - mediatek,mt8365-mipi-tx 36 - const: mediatek,mt8183-mipi-tx [all …]
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H A D | allwinner,sun6i-a31-mipi-dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml# 7 title: Allwinner A31 MIPI D-PHY Controller 19 - const: allwinner,sun6i-a31-mipi-dphy 20 - const: allwinner,sun50i-a100-mipi-dphy 22 - const: allwinner,sun50i-a64-mipi-dphy 23 - const: allwinner,sun6i-a31-mipi-dphy 25 - const: allwinner,sun20i-d1-mipi-dphy 26 - const: allwinner,sun50i-a100-mipi-dphy 51 - "rx" for receiving (e.g. when used with MIPI CSI-2); 52 - "tx" for transmitting (e.g. when used with MIPI DSI). [all …]
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H A D | rockchip-mipi-dphy-rx0.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# 7 title: Rockchip SoC MIPI RX0 D-PHY 14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to 19 const: rockchip,rk3399-mipi-dphy-rx0 23 - description: MIPI D-PHY ref clock 24 - description: MIPI D-PHY RX0 cfg clock 53 * MIPI D-PHY RX0 use registers in "general register files", it 65 mipi_dphy_rx0: mipi-dphy-rx0 { 66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
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H A D | mixel,mipi-dsi-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# 13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the 14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the 18 in either MIPI-DSI PHY mode or LVDS PHY mode. 23 - fsl,imx8mq-mipi-dphy 24 - fsl,imx8qxp-mipi-dphy 59 const: fsl,imx8mq-mipi-dphy 73 const: fsl,imx8qxp-mipi-dphy 89 compatible = "fsl,imx8mq-mipi-dphy";
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/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra114-mipi.yaml | 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml# 7 title: NVIDIA Tegra MIPI pad calibration controller 15 pattern: "^mipi@[0-9a-f]+$" 19 - nvidia,tegra114-mipi 20 - nvidia,tegra210-mipi 21 - nvidia,tegra186-mipi 32 - const: mipi-cal 37 "#nvidia,mipi-calibrate-cells": 38 description: The number of cells in a MIPI calibration specifier. 50 - "#nvidia,mipi-calibrate-cells" [all …]
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/linux/Documentation/devicetree/bindings/display/rockchip/ |
H A D | rockchip,dw-mipi-dsi.yaml | 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml# 7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI 17 - rockchip,px30-mipi-dsi 18 - rockchip,rk3128-mipi-dsi 19 - rockchip,rk3288-mipi-dsi 20 - rockchip,rk3399-mipi-dsi 21 - rockchip,rk3568-mipi-dsi 22 - rockchip,rv1126-mipi-dsi 23 - const: snps,dw-mipi-dsi 74 - $ref: /schemas/display/bridge/snps,dw-mipi-dsi.yaml# [all …]
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/linux/Documentation/devicetree/bindings/media/ |
H A D | nxp,imx-mipi-csi2.yaml | 4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml# 7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver 14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is 27 - fsl,imx7-mipi-csi2 28 - fsl,imx8mm-mipi-csi2 31 - fsl,imx8mp-mipi-csi2 32 - const: fsl,imx8mm-mipi-csi2 45 - description: The MIPI D-PHY clock 60 description: The MIPI D-PHY digital power supply [all …]
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H A D | allwinner,sun6i-a31-mipi-csi2.yaml | 4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml# 7 title: Allwinner A31 MIPI CSI-2 15 - const: allwinner,sun6i-a31-mipi-csi2 17 - const: allwinner,sun8i-v3s-mipi-csi2 18 - const: allwinner,sun6i-a31-mipi-csi2 38 description: MIPI D-PHY 53 description: Input port, connect to a MIPI CSI-2 sensor 101 compatible = "allwinner,sun8i-v3s-mipi-csi2", 102 "allwinner,sun6i-a31-mipi-csi2";
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H A D | allwinner,sun8i-a83t-mipi-csi2.yaml | 4 $id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml# 7 title: Allwinner A83T MIPI CSI-2 14 const: allwinner,sun8i-a83t-mipi-csi2 26 - description: MIPI-specific Clock 33 - const: mipi 45 description: Input port, connect to a MIPI CSI-2 sensor 91 compatible = "allwinner,sun8i-a83t-mipi-csi2"; 98 clock-names = "bus", "mod", "mipi", "misc";
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/linux/include/video/ |
H A D | mipi_display.h | 3 * Defines for Mobile Industry Processor Interface (MIPI(R)) 13 /* MIPI DSI Processor-to-Peripheral transaction types */ 66 /* MIPI DSI Peripheral-to-Processor transaction types */ 78 /* MIPI DCS commands */ 111 MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */ 128 MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ 129 MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */ 130 MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */ 131 MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */ 132 MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */ [all …]
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/linux/Documentation/devicetree/bindings/display/ |
H A D | allwinner,sun6i-a31-mipi-dsi.yaml | 4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml# 7 title: Allwinner A31 MIPI-DSI Controller 17 - allwinner,sun6i-a31-mipi-dsi 18 - allwinner,sun50i-a64-mipi-dsi 19 - allwinner,sun50i-a100-mipi-dsi 21 - const: allwinner,sun20i-d1-mipi-dsi 22 - const: allwinner,sun50i-a100-mipi-dsi 76 - allwinner,sun6i-a31-mipi-dsi 77 - allwinner,sun50i-a100-mipi-dsi 97 - allwinner,sun6i-a31-mipi-dsi [all …]
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/linux/Documentation/admin-guide/media/ |
H A D | imx.rst | 32 camera sensors over Parallel, BT.656/1120, and MIPI CSI-2 buses. 66 - MIPI CSI-2 Receiver for camera sensors with the MIPI CSI-2 bus 84 - Supports parallel, BT.565, and MIPI CSI-2 interfaces. 115 MIPI CSI-2 OV5640 sensor, requires the i.MX6 MIPI CSI-2 receiver. But 117 therefore does not require the MIPI CSI-2 receiver, so it is missing in 137 imx6-mipi-csi2 140 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive 141 the MIPI CSI-2 stream (usually from a MIPI CSI-2 camera sensor). It has 142 four source pads, corresponding to the four MIPI CSI-2 demuxed virtual 146 This entity actually consists of two sub-blocks. One is the MIPI CSI-2 [all …]
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H A D | imx7.rst | 16 - MIPI CSI-2 Receiver 20 MIPI Camera Input ---> MIPI CSI-2 --- > |\ 36 imx-mipi-csi2 39 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel 40 data from MIPI CSI-2 camera sensor. It has one source pad, corresponding to the 48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has 55 can interface directly with Parallel and MIPI CSI-2 buses. It has 256 x 64 FIFO 76 On this platform an OV2680 MIPI CSI-2 module is connected to the internal MIPI 83 media-ctl -l "'ov2680 1-0036':0 -> 'imx7-mipi-csis.0':0[1]" 84 media-ctl -l "'imx7-mipi-csis.0':1 -> 'csi-mux':1[1]" [all …]
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/linux/Documentation/driver-api/soundwire/ |
H A D | summary.rst | 5 SoundWire is a new interface ratified in 2015 by the MIPI Alliance. 58 The MIPI SoundWire specification uses the term 'device' to refer to a Master 69 Programs all the MIPI-defined Slave registers. Represents a SoundWire 77 Driver controlling the Slave device. MIPI-specified registers are controlled 91 Bus implements API to read standard Master MIPI properties and also provides 133 MIPI specification, so Bus calls the "sdw_master_port_ops" callback 141 The MIPI specification requires each Slave interface to expose a unique 154 board-file, ACPI or DT. The MIPI Software specification defines additional 181 For capabilities, Bus implements API to read standard Slave MIPI properties 198 SoundWire MIPI specification 1.1 is available at: [all …]
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/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | intel,keembay-dsi.yaml | 7 title: Intel Keem Bay mipi dsi controller 19 - description: MIPI registers range 23 - const: mipi 27 - description: MIPI DSI clock 28 - description: MIPI DSI econfig clock 29 - description: MIPI DSI config clock 43 description: MIPI DSI input port. 65 mipi-dsi@20900000 { 68 reg-names = "mipi";
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H A D | fsl,imx93-mipi-dsi.yaml | 4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml# 7 title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI 13 There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys 14 Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations 18 - $ref: snps,dw-mipi-dsi.yaml# 22 const: fsl,imx93-mipi-dsi 45 configurations from LCDIF display controller to the MIPI DSI host 46 controller and MIPI DPHY PLL related configurations through PLL SoC 68 compatible = "fsl,imx93-mipi-dsi";
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H A D | lontium,lt9211.yaml | 41 Primary MIPI DSI port-1 for MIPI input or 47 Additional MIPI port-2 for MIPI input or LVDS port-2 54 Primary MIPI DSI port-1 for MIPI output or 60 Additional MIPI port-2 for MIPI output or LVDS port-2
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/linux/Documentation/devicetree/bindings/i3c/ |
H A D | mipi-i3c-hci.yaml | 4 $id: http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml# 7 title: MIPI I3C HCI 16 MIPI I3C Host Controller Interface 18 The MIPI I3C HCI (Host Controller Interface) specification defines 19 a common software driver interface to support compliant MIPI I3C 27 https://www.mipi.org/specifications/i3c-hci 31 const: mipi-i3c-hci 47 compatible = "mipi-i3c-hci";
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/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | mipi-ccs.yaml | 5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml# 8 title: MIPI CCS, SMIA++ and SMIA compliant camera sensors 16 MIPI Alliance; see 17 <URL:https://www.mipi.org/specifications/camera-command-set>. 30 - const: mipi-ccs-1.1 31 - const: mipi-ccs 33 - const: mipi-ccs-1.0 34 - const: mipi-ccs 116 compatible = "mipi-ccs-1.0", "mipi-ccs";
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/linux/Documentation/devicetree/bindings/media/xilinx/ |
H A D | xlnx,csi2rxss.yaml | 7 title: Xilinx MIPI CSI-2 Receiver Subsystem 13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 16 The subsystem consists of a MIPI D-PHY in slave mode which captures the 17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the 20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem. 21 Please note that this bindings includes only the MIPI CSI-2 Rx controller 28 - xlnx,mipi-csi2-rx-subsystem-5.0 118 connects to MIPI CSI-2 source like sensor. 174 compatible = "xlnx,mipi-csi2-rx-subsystem-5.0"; 196 /* MIPI CSI-2 Camera handle */
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/linux/Documentation/driver-api/media/drivers/ccs/ |
H A D | ccs.rst | 7 MIPI CCS camera sensor driver 10 The MIPI CCS camera sensor driver is a generic driver for `MIPI CCS 11 <https://www.mipi.org/specifications/camera-command-set>`_ compliant 19 The MIPI CCS driver supports CCS static data for all compliant devices, 35 vvvv or vv denotes MIPI and SMIA manufacturer IDs respectively, mmmm model ID 41 `CCS tools <https://github.com/MIPI-Alliance/ccs-tools/>`_ is a set of 49 The ccs-regs.asc file contains MIPI CCS register definitions that are used 78 The PLL model implemented by the PLL calculator corresponds to MIPI CCS 1.1.
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/linux/drivers/gpu/drm/panel/ |
H A D | Kconfig | 56 uses 24 bit RGB per pixel. It provides a MIPI DSI interface to 67 24 bit RGB per pixel. It provides a MIPI DSI interface to 78 resolution and uses 24 bit RGB per pixel. It provides a MIPI DSI 107 The panel has a resolution of 1080x2246. It provides a MIPI DSI 117 KD35T133 controller for 320x480 LCD panels with MIPI-DSI 127 4-lane 800x1280 MIPI DSI panel. 130 tristate "Feiyang FY07024DI26A30-D MIPI-DSI LCD panel" 136 Feiyang FY07024DI26A30-D MIPI-DSI interface. 177 tristate "HIMAX HX8394 MIPI-DSI LCD panels" 184 720x1440 TFT LCD panel that uses a MIPI-DSI interface. [all …]
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/linux/drivers/gpu/drm/bridge/ |
H A D | Kconfig | 36 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge" 43 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone. 45 It has a flexible configuration of MIPI DSI signal input 213 tristate "Northwest Logic MIPI DSI Host controller" 226 This enables the Northwest Logic MIPI DSI Host controller as 247 tristate "Parade PS8640 MIPI DSI to eDP Converter" 258 MIPI DSI to eDP converter 261 tristate "Samsung MIPI DSIM bridge driver" 270 The Samsung MIPI DSIM bridge controller driver. 271 This MIPI DSIM bridge can be found it on Exynos SoCs and [all …]
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