| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | samsung,mipi-video-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,mipi-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC MIPI CSIS/DSIM DPHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the
16 PHY specifier identifies the PHY and its meaning is as follows::
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| H A D | mediatek,dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19 pattern: "^dsi-phy@[0-9a-f]+$"
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| H A D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel DSI PHY for i.MX8
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
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| H A D | allwinner,sun6i-a31-mipi-dphy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
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| H A D | rockchip-mipi-dphy-rx0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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| H A D | amlogic,axg-mipi-dphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic AXG MIPI D-PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,axg-mipi-dphy
24 clock-names:
26 - const: pclk
31 reset-names:
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| H A D | amlogic,meson-axg-mipi-pcie-analog.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic AXG shared MIPI/PCIE analog PHY
10 - Remi Pommarel <repk@triplefau.lt>
14 const: amlogic,axg-mipi-pcie-analog-phy
16 "#phy-cells":
20 - compatible
21 - "#phy-cells"
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| H A D | amlogic,g12a-mipi-dphy-analog.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic G12A MIPI analog PHY
10 - Neil Armstrong <narmstrong@baylibre.com>
14 const: amlogic,g12a-mipi-dphy-analog
16 "#phy-cells":
20 - compatible
21 - "#phy-cells"
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | nxp,imx-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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| H A D | allwinner,sun6i-a31-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI CSI-2
10 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
15 - const: allwinner,sun6i-a31-mipi-csi2
16 - items:
17 - const: allwinner,sun8i-v3s-mipi-csi2
18 - const: allwinner,sun6i-a31-mipi-csi2
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| H A D | nxp,imx8mq-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
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| H A D | imx.txt | 5 ---------------------------
12 - compatible : "fsl,imx-capture-subsystem";
13 - ports : Should contain a list of phandles pointing to camera
18 capture-subsystem {
19 compatible = "fsl,imx-capture-subsystem";
25 --------------
27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29 combined with a D-PHY core mixed into the same register block. In
30 addition this device consists of an i.MX-specific "CSI2IPU gasket"
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| /linux/drivers/phy/rockchip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
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| /linux/drivers/phy/amlogic/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Amlogic platforms
6 tristate "Meson8, Meson8b and Meson8m2 HDMI TX PHY driver"
16 tristate "Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY driver"
29 tristate "Meson GXL and GXM USB2 PHY drivers"
41 tristate "Meson G12A MIPI Analog DPHY driver"
48 Enable this to support the Meson MIPI Analog DPHY found in Meson G12A
53 tristate "Meson G12A USB2 PHY driver"
64 tristate "Meson G12A USB3+PCIE Combo PHY driver"
70 Enable this to support the Meson USB3 + PCIE Combo PHY found
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| H A D | phy-meson-axg-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Meson AXG MIPI DPHY driver
20 #include <linux/phy/phy.h>
23 /* [31] soft reset for the phy.
30 * [25] mipi dsi pll clock selection.
32 * [12] mipi HSbyteclk enable.
33 * [11] mipi divider clk selection.
34 * 1: select the mipi DDRCLKHS from clock divider.
36 * [10] mipi clock divider control.
38 * [9] mipi divider output enable.
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| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_PHY_MESON8_HDMI_TX) += phy-meson8-hdmi-tx.o
3 obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
4 obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
5 obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
6 obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
7 obj-$(CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG) += phy-meson-g12a-mipi-dphy-analog.o
8 obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
9 obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG) += phy-meson-axg-mipi-pcie-analog.o
10 obj-$(CONFIG_PHY_MESON_AXG_MIPI_DPHY) += phy-meson-axg-mipi-dphy.o
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| H A D | phy-meson-g12a-mipi-dphy-analog.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Meson G12A MIPI DSI Analog PHY
12 #include <linux/phy/phy.h>
18 #include <dt-bindings/phy/phy.h>
40 struct phy *phy; member
45 static int phy_g12a_mipi_dphy_analog_configure(struct phy *phy, in phy_g12a_mipi_dphy_analog_configure() argument
48 struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy); in phy_g12a_mipi_dphy_analog_configure()
51 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); in phy_g12a_mipi_dphy_analog_configure()
55 memcpy(&priv->config, opts, sizeof(priv->config)); in phy_g12a_mipi_dphy_analog_configure()
60 static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy) in phy_g12a_mipi_dphy_analog_power_on() argument
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| /linux/Documentation/devicetree/bindings/display/rockchip/ |
| H A D | rockchip,dw-mipi-dsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3128-mipi-dsi
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | samsung,mipi-dsim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung MIPI DSIM bridge controller
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
15 Samsung MIPI DSIM bridge controller can be found it on Exynos
21 - enum:
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| H A D | renesas,dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
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| /linux/Documentation/devicetree/bindings/soc/samsung/ |
| H A D | exynos-pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | allwinner,sun6i-a31-mipi-dsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - enum:
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
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| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "phy-mtk-mipi-dsi.h"
18 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate); in mtk_mipi_tx_pll_set_rate()
20 mipi_tx->data_rate = rate; in mtk_mipi_tx_pll_set_rate()
30 return mipi_tx->data_rate; in mtk_mipi_tx_pll_recalc_rate()
33 static int mtk_mipi_tx_power_on(struct phy *phy) in mtk_mipi_tx_power_on() argument
35 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); in mtk_mipi_tx_power_on()
39 ret = clk_prepare_enable(mipi_tx->pll_hw.clk); in mtk_mipi_tx_power_on()
44 mipi_tx->driver_data->mipi_tx_enable_signal(phy); in mtk_mipi_tx_power_on()
48 static int mtk_mipi_tx_power_off(struct phy *phy) in mtk_mipi_tx_power_off() argument
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| /linux/drivers/phy/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Samsung platforms
6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
25 bool "Exynos PCIe PHY driver"
29 Enable PCIe PHY support for Exynos SoC series.
30 This driver provides PHY interface for Exynos PCIe controller.
33 tristate "Exynos SoC series UFS PHY driver"
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| /linux/Documentation/devicetree/bindings/soc/imx/ |
| H A D | fsl,imx8mp-media-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#address-cells':
29 '#size-cells':
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