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/linux/include/drm/
H A Ddrm_mipi_dbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * MIPI Display Bus Interface (DBI) LCD controller support
23 * struct mipi_dbi - MIPI DBI interface
70 * @tx_buf9: Buffer used for Option 1 9-bit conversion
81 * struct mipi_dbi_dev - MIPI DBI device
100 * @mode: Fixed display mode
102 struct drm_display_mode mode; member
147 * @dbi: MIPI DBI interface
170 const struct drm_display_mode *mode,
174 const struct drm_display_mode *mode, unsigned int rotation);
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/linux/Documentation/devicetree/bindings/phy/
H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
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H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
22 corresponding mode names.
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/linux/sound/soc/sdca/
H A Dsdca_functions.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
5 * The MIPI SDCA specification is available for public downloads at
6 * https://www.mipi.org/mipi-sdca-v1-0-download
25 * Should be long enough to encompass all the MIPI DisCo properties.
56 return -EINVAL; in patch_sdca_function_type()
94 struct device *dev = &adev->dev; in find_sdca_function()
102 if (sdca_data->num_functions >= SDCA_MAX_FUNCTION_COUNT) { in find_sdca_function()
104 return -EINVAL; in find_sdca_function()
107 ret = acpi_get_local_u64_address(adev->handle, &addr); in find_sdca_function()
113 return -ENODEV; in find_sdca_function()
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/linux/drivers/gpu/drm/tiny/
H A Dpanel-mipi-dbi.c1 // SPDX-License-Identifier: GPL-2.0
3 * DRM driver for MIPI DBI compatible display panels
61 if (strcmp(format_name, format->name)) in panel_mipi_dbi_get_format()
64 formats[0] = format->fourcc; in panel_mipi_dbi_get_format()
65 *bpp = format->bpp; in panel_mipi_dbi_get_format()
71 return -EINVAL; in panel_mipi_dbi_get_format()
90 * MIPI commands to execute when the display pipeline is enabled.
98 * parameter: delay in miliseconds (the No Operation command is part of the MIPI Display
124 const struct panel_mipi_dbi_config *config = (struct panel_mipi_dbi_config *)fw->data; in panel_mipi_dbi_check_commands()
126 size_t size = fw->size, commands_len; in panel_mipi_dbi_check_commands()
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/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-mipi-dbi-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DBI SPI Panel
10 - Noralf Trønnes <noralf@tronnes.org>
13 This binding is for display panels using a MIPI DBI compatible controller
14 in SPI mode.
16 The MIPI Alliance Standard for Display Bus Interface defines the electrical
23 - Power:
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/linux/drivers/soundwire/
H A Dmipi_disco.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
5 * MIPI Discovery And Configuration (DisCo) Specification for SoundWire
47 * sdw_master_read_prop() - Read Master properties
52 struct sdw_master_prop *prop = &bus->prop; in sdw_master_read_prop()
60 device_property_read_u32(bus->dev, in sdw_master_read_prop()
61 "mipi-sdw-sw-interface-revision", in sdw_master_read_prop()
62 &prop->revision); in sdw_master_read_prop()
66 "mipi-sdw-link-%d-subproperties", bus->link_id); in sdw_master_read_prop()
68 link = device_get_named_child_node(bus->dev, name); in sdw_master_read_prop()
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/linux/Documentation/devicetree/bindings/soundwire/
H A Dqcom,soundwire.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - enum:
20 - qcom,soundwire-v1.3.0
21 - qcom,soundwire-v1.5.0
22 - qcom,soundwire-v1.5.1
23 - qcom,soundwire-v1.6.0
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
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H A Dfsl,imx93-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI
10 - Liu Ying <victor.liu@nxp.com>
13 There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys
14 Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations
15 and extensions to them are controlled by i.MX93 media blk-ctrl.
18 - $ref: snps,dw-mipi-dsi.yaml#
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/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
18 or parallel. The hardware is capable of transmitting and receiving MIPI
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
42 Boot mode of the THP7312, reflecting the value of the BOOT[0] pin strap.
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
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H A Dmaxim,max96717.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MAX96717 CSI-2 to GMSL2 Serializer
11 - Julien Massot <julien.massot@collabora.com>
14 The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located deserializer using industry-standard coax or STP
19 interconnects. The device cans operate in pixel or tunnel mode. In pixel mode
20 the MAX96717 can select the MIPI datatype, while the tunnel mode forward all the MIPI
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/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774a1-hihope-rzg2m-ex-mipi-2.1.dts1 // SPDX-License-Identifier: GPL-2.0
4 * connected with aistarvision-mipi-v2-adapter board
9 /dts-v1/;
10 #include "r8a774a1-hihope-rzg2m-ex.dts"
11 #include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
14 model = "HopeRun HiHope RZ/G2M with sub board connected with aistarvision-mipi-v2-adapter board";
15 compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
19 * On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode.
21 * imx219 as the imx219 endpoint driver supports only 2 lane mode.
/linux/drivers/gpu/drm/tegra/
H A Dmipi-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
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/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-csi-0-5.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek MIPI CSI v0.5 driver
9 #include <dt-bindings/phy/phy.h>
19 #include "phy-mtk-io.h"
20 #include "phy-mtk-mipi-csi-0-5-rx-reg.h"
29 u32 mode; member
76 void __iomem *base = port->base; in mtk_mipi_phy_power_on()
79 * The driver currently supports DPHY and CD-PHY phys, in mtk_mipi_phy_power_on()
80 * but the only mode supported is DPHY, in mtk_mipi_phy_power_on()
81 * so CD-PHY capable phys must be configured in DPHY mode in mtk_mipi_phy_power_on()
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/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
71 /* 0x61190 if MIPI */
78 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
82 /* if MIPI, 0x0000 if LVDS */
84 /* 0: Type-1, */
85 /* 1: Type-2, */
86 /* 2: Type-3, */
87 /* 3: Type-4 */
94 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #define DRIVER_NAME "meson-dw-mipi-dsi"
34 #define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
45 const struct drm_display_mode *mode; member
61 mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); in meson_dw_mipi_dsi_hw_init()
64 0, mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); in meson_dw_mipi_dsi_hw_init()
69 mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL); in meson_dw_mipi_dsi_hw_init()
72 writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD); in meson_dw_mipi_dsi_hw_init()
82 ret = clk_set_rate(mipi_dsi->bit_clk, in dw_mipi_dsi_phy_init()
83 mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate); in dw_mipi_dsi_phy_init()
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/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
18 * of the D-PHY specification (v1.2).
29 return -EINVAL; in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
42 cfg->clk_prepare = 38000; in phy_mipi_dphy_calc_config()
43 cfg->clk_settle = 95000; in phy_mipi_dphy_calc_config()
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/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
3 * Meson AXG MIPI DPHY driver
30 * [25] mipi dsi pll clock selection.
32 * [12] mipi HSbyteclk enable.
33 * [11] mipi divider clk selection.
34 * 1: select the mipi DDRCLKHS from clock divider.
36 * [10] mipi clock divider control.
38 * [9] mipi divider output enable.
39 * [8] mipi divider counter enable.
44 * [3] force data byte lane in stop mode.
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 64) : \
66 ((x) - 128))
67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
91 bool is_combo; /* MIPI DPHY and LVDS PHY combo */
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/linux/arch/arm/mach-imx/
H A Dmach-imx51.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
34 /* setup MIPI module to legacy mode */ in imx51_ipu_mipi_setup()
37 /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ in imx51_ipu_mipi_setup()
48 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-m4if"); in imx51_m4if_setup()
76 imx_aips_allow_unprivileged_access("fsl,imx51-aipstz"); in imx51_dt_init()
/linux/include/linux/soundwire/
H A Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
27 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
88 * enum sdw_slave_status - Slave status
106 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
107 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepar
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/linux/include/media/drv-intf/
H A Dexynos-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
12 #include <media/media-entity.h>
13 #include <media/v4l2-dev.h>
14 #include <media/v4l2-mediabus.h>
37 /* Camera MIPI-CSI2 serial bus */
43 /* FIFO link from FIMC-IS */
62 * struct fimc_source_info - video source description required for the host
66 * @sensor_bus_type: image sensor bus type, MIPI, ITU-R BT.601 etc.
68 * @mux_id: FIMC camera interface multiplexer index (separate for MIPI and ITU)
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