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Searched +full:mipi +full:- +full:dsi2 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/rockchip/
H A Ddw-mipi-dsi2-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
12 #include <linux/media-bus-format.h>
85 static void grf_field_write(struct dw_mipi_dsi2_rockchip *dsi2, enum grf_reg_fields index, in grf_field_write() argument
88 const struct dsigrf_reg *field = &dsi2->cdata->grf_regs[index]; in grf_field_write()
93 regmap_write(dsi2->grf_regmap, field->offset, in grf_field_write()
94 (val << field->lsb) | (GENMASK(field->msb, field->lsb) << 16)); in grf_field_write()
104 struct dw_mipi_dsi2_rockchip *dsi2 = priv_data; in dw_mipi_dsi2_phy_power_on() local
107 ret = phy_set_mode(dsi2->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi2_phy_power_on()
109 dev_err(dsi2->dev, "Failed to set phy mode: %d\n", ret); in dw_mipi_dsi2_phy_power_on()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
78 bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
83 enable MIPI DSI on RK3288 or RK3399 based SoC, you should
87 bool "Rockchip specific extensions for Synopsys DW MIPI DSI2"
91 for the Synopsys DesignWare DSI2 driver. If you want to
92 enable MIPI DSI on RK3576 or RK3588 based SoC, you should
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
9 rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o
10 rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
11 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
12 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
13 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
14 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI_QP) += dw_hdmi_qp-rockchip.o
15 rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
16 rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI2) += dw-mipi-dsi2-rockchip.o
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H A Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
274 /* dual-channel */
282 /* being a phy for other mipi hosts */
365 return -EINVAL; in max_mbps_to_parameter()
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,rk3588-mipi-dsi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3588-mipi-dsi2
26 clock-names:
28 - const: pclk
29 - const: sys
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi2.c1 // SPDX-License-Identifier: GPL-2.0+
6 * This generic Synopsys DesignWare MIPI DSI2 host driver is based on the
7 * Rockchip version from rockchip/dw-mipi-dsi2.c converted to use bridge APIs.
13 #include <linux/media-bus-format.h>
69 #define PHY_LANES(x) FIELD_PREP(GENMASK(5, 4), (x) - 1)
220 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) in cri_fifos_wait_avail() argument
226 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, sts, in cri_fifos_wait_avail()
229 dev_err(dsi2->dev, "command interface is busy\n"); in cri_fifos_wait_avail()
236 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_set_vid_mode() argument
241 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) in dw_mipi_dsi2_set_vid_mode()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
3 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
4 obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
5 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
6 obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
8 obj-$(CONFIG_DRM_DW_HDMI_QP) += dw-hdmi-qp.o
10 obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
11 obj-$(CONFIG_DRM_DW_MIPI_DSI2) += dw-mipi-dsi2.o
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-media-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#address-cells':
29 '#size-cells':
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/linux/drivers/pmdomain/imx/
H A Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
51 * which is used to control the reset for the MIPI Phy.
53 * an if-statement should be used before setting and clearing this
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
89 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
93 ret = pm_runtime_get_sync(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
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