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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun6i-a31-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - enum:
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
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H A Dmipi-dsi-bus.txt1 MIPI DSI (Display Serial Interface) busses
4 The MIPI Display Serial Interface specifies a serial bus and a protocol for
6 define the syntax used to represent a DSI bus in a device tree.
8 This document describes DSI bus-specific properties only or defines existing
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
12 set of properties that characterize the bus. Child nodes describe individual
13 peripherals on that bus.
15 The following assumes that only a single peripheral is connected to a DSI
18 DSI host
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H A Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 encoder clock source and contains additional TV TCON and DSI gates.
22 / [0] TCON-LCD0
23 | \ MIPI DSI
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
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H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
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H A Dfsl,imx8mn-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MN DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mn-disp-blk-ctrl
21 - const: syscon
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H A Dfsl,imx8mp-media-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#address-cells':
29 '#size-cells':
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
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H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DSI to eDP Video Format Converter
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
28 powerdown-gpios:
32 reset-gpios:
36 vdd12-supply:
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H A Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Douglas Anderson <dianders@chromium.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
37 vccio-supply:
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H A Dadi,adv7533.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 - $ref: /schemas/sound/dai-common.yaml#
18 conversion, S/PDIF, CEC and HDCP. The transmitter input is MIPI DSI.
23 - adi,adv7533
24 - adi,adv7535
33 device on the I2C bus. The main address is mandatory, others are
38 reg-names:
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/linux/drivers/pmdomain/imx/
H A Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
51 * which is used to control the reset for the MIPI Phy.
53 * an if-statement should be used before setting and clearing this
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
89 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
92 /* make sure bus domain is awake */ in imx8m_blk_ctrl_power_on()
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
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/linux/Documentation/devicetree/bindings/phy/
H A Dallwinner,sun6i-a31-mipi-dphy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
24 dispc, dsi, hdmi and rfbi.
34 <debugfs>/omapdss/dsi_irq for DSI interrupts.
46 OMAP Video Encoder support for S-Video and composite TV-out.
71 SDI is a high speed one-way display serial bus between the host
75 bool "DSI support"
77 MIPI DSI (Display Serial Interface) support.
79 DSI is a high speed half-duplex serial interface between the host
82 See https://www.mipi.org/ for DSI specifications.
/linux/drivers/gpu/drm/omapdrm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 dispc, dsi, hdmi and rfbi.
46 <debugfs>/omapdss/dsi_irq for DSI interrupts.
58 OMAP Video Encoder support for S-Video and composite TV-out.
93 SDI is a high speed one-way display serial bus between the host
97 bool "DSI support"
101 MIPI DSI (Display Serial Interface) support.
103 DSI is a high speed half-duplex serial interface between the host
106 See http://www.mipi.org/ for DSI specifications.
/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
64 else if (client == ctx->i2c.rx_p0_client) in i2c_access_workaround()
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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun8i-a23.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
25 #include "ccu-sun8i-a23-a33.h"
39 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
50 * With sigma-delta modulation for fractional-N on the audio PLL,
64 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
86 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
98 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
107 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
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H A Dccu-sun8i-a33.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
37 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
84 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
96 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
105 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
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