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Searched +full:mipi +full:- +full:csi (Results 1 – 25 of 118) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/
H A D	xlnx,csi2rxss.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx MIPI CSI-2 Receiver Subsystem 10 - Vishal Sagar <vishal.sagar@amd.com> 13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 16 The subsystem consists of a MIPI D-PHY in slave mode which captures the 17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the 20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem. 21 Please note that this bindings includes only the MIPI CSI-2 Rx controller [all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A D	fsl,imx8mm-disp-blk-ctrl.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8MM DISP blk-ctrl 10 - Lucas Stach <l.stach@pengutronix.de> 13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to 14 the NoC and ensuring proper power sequencing of the display and MIPI CSI 20 - const: fsl,imx8mm-disp-blk-ctrl 21 - const: syscon [all …]`
H A D	fsl,imx8mn-disp-blk-ctrl.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8MN DISP blk-ctrl 10 - Lucas Stach <l.stach@pengutronix.de> 13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to 14 the NoC and ensuring proper power sequencing of the display and MIPI CSI 20 - const: fsl,imx8mn-disp-blk-ctrl 21 - const: syscon [all …]`
/freebsd/sys/contrib/device-tree/Bindings/media/
H A D	nxp,imx-mipi-csi2.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver 10 - Rui Miguel Silva <rmfrfs@gmail.com> 11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 13 description: \|- 14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is [all …]
H A D	nxp,imx7-mipi-csi2.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver 10 - Rui Miguel Silva <rmfrfs@gmail.com> 11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 13 description: \|- 14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is [all …]
H A D	allwinner,sun8i-a83t-mipi-csi2.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A83T MIPI CSI-2 10 - Paul Kocialkowski <paul.kocialkowski@bootlin.com> 14 const: allwinner,sun8i-a83t-mipi-csi2 24 - description: Bus Clock 25 - description: Module Clock 26 - description: MIPI-specific Clock [all …]`
H A D	imx.txt	5 --------------------------- 12 - compatible : "fsl,imx-capture-subsystem"; 13 - ports : Should contain a list of phandles pointing to camera 18 capture-subsystem { 19 compatible = "fsl,imx-capture-subsystem"; 25 -------------- 27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX 28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core 29 combined with a D-PHY core mixed into the same register block. In 30 addition this device consists of an i.MX-specific "CSI2IPU gasket" [all …]
H A D	allwinner,sun6i-a31-mipi-csi2.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A31 MIPI CSI-2 10 - Paul Kocialkowski <paul.kocialkowski@bootlin.com> 15 - const: allwinner,sun6i-a31-mipi-csi2 16 - items: 17 - const: allwinner,sun8i-v3s-mipi-csi2 18 - const: allwinner,sun6i-a31-mipi-csi2 [all …]`
H A D	video-interfaces.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/video-interface [all...]`
H A D	renesas,rzg2l-csi2.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L 15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction 21 - enum: 22 - renesas,r9a07g043-csi2 # RZ/G2UL [all …]
H A D	nxp,imx8mq-mipi-csi2.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8MQ MIPI CSI-2 receiver 10 - Martin Kepplinger <martin.kepplinger@puri.sm> 12 description: \|- 13 This binding covers the CSI-2 RX PHY and host controller included in the 20 - fsl,imx8mq-mipi-csi2 27 - description: core is the RX Controller Core Clock input. This clock [all …]`
H A D	samsung,exynos4210-csis.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-csis.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS) 10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 11 - Sylwester Nawrocki <s.nawrocki@samsung.com> 16 - samsung,s5pv210-csis 17 - samsung,exynos4210-csis 18 - samsung,exynos4212-csis [all …]`
H A D	imx7-mipi-csi2.txt	1 Freescale i.MX7 Mipi CSI2 5 -------------- 7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is 8 compatible with previous version of Samsung D-phy. 12 - compatible : "fsl,imx7-mipi-csi2"; 13 - reg : base address and length of the register set for the device; 14 - interrupts : should contain MIPI CSIS interrupt; 15 - clocks : list of clock specifiers, see 16 Documentation/devicetree/bindings/clock/clock-bindings.txt for details; 17 - clock-names : must contain "pclk", "wrap" and "phy" entries, matching [all …]
H A D	nxp,imx8-isi.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI 17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. 22 - fsl,imx8mn-isi 23 - fsl,imx8mp-isi 24 - fsl,imx93-isi [all …]`
H A D	samsung-mipi-csis.txt	1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS) 2 ------------------------------------------------------------- 6 - compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110), 7 "samsung,exynos4210-csis" for Exynos4210 (S5PC210), 8 "samsung,exynos4212-csis" for Exynos4212/Exynos4412, 9 "samsung,exynos5250-csis" for Exynos5250; 10 - reg : offset and length of the register set for the device; 11 - interrupts : should contain MIPI CSIS interrupt; the format of the 13 - bus-width : maximum number of data lanes supported (SoC specific); 14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V); [all …]
H A D	cdns,csi2rx.txt	1 Cadence MIPI-CSI2 RX controller 4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI 8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible 9 - reg: base address and size of the memory mapped region 10 - clocks: phandles to the clocks driving the controller 11 - clock-names: must contain: 14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream 18 - phys: phandle to the external D-PHY, phy-names must be provided 19 - phy-names: must contain "dphy", if the implementation uses an 20 external D-PHY [all …]
H A D	cdns,csi2tx.txt	1 Cadence MIPI-CSI2 TX controller 4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to 5 4 CSI lanes in output, and up to 4 different pixel streams in input. 8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3" 9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1 10 - reg: base address and size of the memory mapped region 11 - clocks: phandles to the clocks driving the controller 12 - clock-names: must contain: 15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream 19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set [all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A D	tc358743.txt	1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge 3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts 4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C. 8 - compatible: value should be "toshiba,tc358743" 9 - clocks, clock-names: should contain a phandle link to the reference clock 14 - reset-gpios: gpio phandle GPIO connected to the reset pin 15 - interrupts: GPIO connected to the interrupt pin 16 - data-lanes: should be <1 2 3 4> for four-lane operation, 17 or <1 2> for two-lane operation 18 - clock-lanes: should be <0> [all …]
H A D	toshiba,tc358746.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...]`
H A D	isil,isl79987.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Intersil ISL79987 Analog to MIPI CSI-2 decoder 10 - Michael Tretter <m.tretter@pengutronix.de> 11 - Marek Vasut <marex@denx.de> 14 The Intersil ISL79987 is an analog to MIPI CSI-2 decoder which is capable of 15 receiving up to four analog stream and multiplexing them into up to four MIPI 16 CSI-2 virtual channels, using one MIPI clock lane and 1/2 data lanes. 21 - isil,isl79987 [all …]
H A D	ov5640.txt	1 * Omnivision OV5640 MIPI CSI-2 / parallel sensor 4 - compatible: should be "ovti,ov5640" 5 - clocks: reference to the xclk input clock. 6 - clock-names: should be "xclk". 7 - DOVDD-supply: Digital I/O voltage supply, 1.8 volts 8 - AVDD-supply: Analog voltage supply, 2.8 volts 9 - DVDD-supply: Digital core voltage supply, 1.5 volts 12 - reset-gpios: reference to the GPIO connected to the reset pin, if any. 14 - powerdown-gpios: reference to the GPIO connected to the powerdown pin, 16 - rotation: as defined in [all …]
H A D	mipi-ccs.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2014--2020 Intel Corporation 4 --- 5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MIPI CCS, SMIA++ and SMIA compliant camera sensors 11 - Sakari Ailus <sakari.ailus@linux.intel.com> 16 MIPI Alliance; see 17 <URL:https://www.mipi.org/specifications/camera-command-set>. 24 Documentation/devicetree/bindings/media/video-interfaces.txt . [all …]
H A D	thine,thp7312.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Paul Elder <paul.elder@@ideasonboard.com> 17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2 18 or parallel. The hardware is capable of transmitting and receiving MIPI 23 - $ref: /schemas/media/video-interface-devices.yaml# 36 thine,boot-mode: 43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from 46 reset-gpios: [all …]`
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A D	rockchip-inno-csi-dphy.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/rockchip-inn [all...]`
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A D	renesas,dsi-csi2-tx.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas 14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up 20 - renesas,r8a779a0-dsi-csi2-tx # for V3U 21 - renesas,r8a779g0-dsi-csi2-tx # for V4H [all …]

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