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/linux/drivers/gpu/drm/radeon/
H A Ddce3_1_afmt.c2 * Copyright 2013 Advanced Micro Devices, Inc.
34 struct radeon_device *rdev = encoder->dev->dev_private; in dce3_2_afmt_hdmi_write_speaker_allocation()
52 struct radeon_device *rdev = encoder->dev->dev_private; in dce3_2_afmt_dp_write_speaker_allocation()
71 struct radeon_device *rdev = encoder->dev->dev_private; in dce3_2_afmt_write_sad_regs()
90 int max_channels = -1; in dce3_2_afmt_write_sad_regs()
96 if (sad->format == eld_reg_to_type[i][1]) { in dce3_2_afmt_write_sad_regs()
97 if (sad->channels > max_channels) { in dce3_2_afmt_write_sad_regs()
98 value = MAX_CHANNELS(sad->channels) | in dce3_2_afmt_write_sad_regs()
99 DESCRIPTOR_BYTE_2(sad->byte2) | in dce3_2_afmt_write_sad_regs()
100 SUPPORTED_FREQUENCIES(sad->freq); in dce3_2_afmt_write_sad_regs()
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H A Devergreen_hdmi.c2 * Copyright 2008 Advanced Micro Devices, Inc.
72 struct drm_device *dev = encoder->dev; in evergreen_hdmi_update_acr()
73 struct radeon_device *rdev = dev->dev_private; in evergreen_hdmi_update_acr()
76 if (encoder->crtc) { in evergreen_hdmi_update_acr()
77 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in evergreen_hdmi_update_acr()
78 bpc = radeon_crtc->bpc; in evergreen_hdmi_update_acr()
89 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
90 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
92 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
93 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
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H A Dradeon_audio.c2 * Copyright 2014 Advanced Micro Devices, Inc.
48 (0x5e00 - 0x5e00),
49 (0x5e18 - 0x5e00),
50 (0x5e30 - 0x5e00),
51 (0x5e48 - 0x5e00),
52 (0x5e60 - 0x5e00),
53 (0x5e78 - 0x5e00),
54 (0x5e90 - 0x5e00),
198 if (rdev->mode_info.mode_config_initialized) { in radeon_audio_enable()
199 list_for_each_entry(encoder, &rdev_to_drm(rdev)->mode_config.encoder_list, head) { in radeon_audio_enable()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_psr.c1 // SPDX-License-Identifier: MIT
3 * Copyright 2021 Advanced Micro Devices, Inc.
35 struct dc *dc = link->ctx->dc; in link_supports_psrsu()
37 if (!dc->caps.dmcub_support) in link_supports_psrsu()
40 if (dc->ctx->dce_version < DCN_VERSION_3_1) in link_supports_psrsu()
46 if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP || in link_supports_psrsu()
47 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) in link_supports_psrsu()
50 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED && in link_supports_psrsu()
51 !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) in link_supports_psrsu()
57 /* Temporarily disable PSR-SU to avoid glitches */ in link_supports_psrsu()
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H A Damdgpu_dm_crtc.c1 // SPDX-License-Identifier: MIT
3 * Copyright 2022 Advanced Micro Devices, Inc.
43 struct drm_crtc *crtc = &acrtc->base; in amdgpu_dm_crtc_handle_vblank()
44 struct drm_device *dev = crtc->dev; in amdgpu_dm_crtc_handle_vblank()
49 spin_lock_irqsave(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
51 /* Send completion event for cursor-only commits */ in amdgpu_dm_crtc_handle_vblank()
52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in amdgpu_dm_crtc_handle_vblank()
53 drm_crtc_send_vblank_event(crtc, acrtc->event); in amdgpu_dm_crtc_handle_vblank()
55 acrtc->event = NULL; in amdgpu_dm_crtc_handle_vblank()
58 spin_unlock_irqrestore(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
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H A Damdgpu_dm_ism.c1 // SPDX-License-Identifier: MIT
3 * Copyright 2026 Advanced Micro Devices, Inc.
37 * dm_ism_next_state - Get next state based on current state and event
132 const struct amdgpu_dm_ism_config *config = &ism->config; in dm_ism_get_sso_delay()
139 if (!config->sso_num_frames) in dm_ism_get_sso_delay()
142 v_total = stream->timing.v_total; in dm_ism_get_sso_delay()
143 h_total = stream->timing.h_total; in dm_ism_get_sso_delay()
146 stream->timing.pix_clk_100hz); in dm_ism_get_sso_delay()
147 sso_delay_ns = config->sso_num_frames * one_frame_ns; in dm_ism_get_sso_delay()
153 * dm_ism_get_idle_allow_delay - Calculate hysteresis-based idle allow delay
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/linux/tools/usb/
H A Dhcd-tests.sh2 # SPDX-License-Identifier: GPL-2.0
6 # - control: any device can do this
7 # - out, in: out needs 'bulk sink' firmware, in needs 'bulk src'
8 # - iso-out, iso-in: out needs 'iso sink' firmware, in needs 'iso src'
9 # - halt: needs bulk sink+src, tests halt set/clear from host
10 # - unlink: needs bulk sink and/or src, test HCD unlink processing
11 # - loop: needs firmware that will buffer N transfers
25 # - include unlink tests
26 # - add some ${RANDOM}ness
27 # - connect several devices concurrently (same HC)
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/linux/include/uapi/linux/can/
H A Disotp.h1 /* SPDX-License-Identifier: ((GPL-2.0-only WITH Linux-syscall-note) OR BSD-3-Clause) */
5 * Definitions for ISO 15765-2 CAN transport protocol sockets
65 /* ignore received CF frames which */
98 /* 0x00 - 0x7F : 0 - 127 ms */
99 /* 0x80 - 0xF0 : reserved */
100 /* 0xF1 - 0xF9 : 100 us - 900 us */
101 /* 0xFA - 0xFF : reserved */
111 /* CAN_MTU (16) -> standard CAN 2.0 */
112 /* CANFD_MTU (72) -> CAN FD frame */
138 #define CAN_ISOTP_SF_BROADCAST 0x0800 /* 1-to-N functional addressing */
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/linux/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
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/linux/drivers/accel/amdxdna/
H A Daie2_solver.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
33 u32 fps; /* Frames per second */
74 * Power levels 0 - n, is a step increase in system frequencies
118 * xrsm_init() - Register resource solver. Resource solver client needs
130 * xrs_allocate_resource() - Request to allocate resources for a given context
149 * xrs_release_resource() - Request to free resources for a given context.
/linux/drivers/pci/controller/
H A Dpci-xgene-msi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene MSI Driver
5 * Copyright (c) 2014, Applied Micro Circuits Corporation
16 #include <linux/irqchip/irq-msi-lib.h>
49 * X-Gene v1 has 16 frames of MSI termination registers MSInIRx, where n is
94 return readl_relaxed(msi->msi_regs + MSI_IR0 + in xgene_msi_ir_read()
102 return readl_relaxed(msi->msi_regs + MSI_INT0 + in xgene_msi_int_read()
109 * atomically), we statically partitions the MSI frames between CPUs. Given
110 * that XGene-1 has 8 CPUs, each CPU gets two frames assigned to it
118 * - hwirq[7]::cpu[2:0] is the target frame number (n in MSInIRx)
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_psr.c2 * Copyright 2019 Advanced Micro Devices, Inc.
115 if (dc_wake_and_execute_gpint(dmub->ctx, DMUB_GPINT__GET_PSR_STATE, panel_inst, &raw_state, in dmub_psr_get_state()
143 struct dc_context *dc = dmub->ctx; in dmub_psr_set_version()
145 if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) in dmub_psr_set_version()
151 switch (stream->link->psr_settings.psr_version) { in dmub_psr_set_version()
182 struct dc_context *dc = dmub->ctx; in dmub_psr_enable()
199 dc_wake_and_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); in dmub_psr_enable()
202 * Exit PSR may need to wait 1-2 frames to power up. Timeout after at in dmub_psr_enable()
203 * least a few frames. Should never hit the max retry assert below. in dmub_psr_enable()
217 /* must *not* be fsleep - this can be called from high irq levels */ in dmub_psr_enable()
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/linux/drivers/gpu/drm/amd/display/modules/freesync/
H A Dfreesync.c2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
44 /* Number of consecutive frames to check before entering/exiting fixed refresh */
72 core_freesync->dc = dc; in mod_freesync_create()
73 return &core_freesync->public; in mod_freesync_create()
120 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
121 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
128 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; in calc_max_hardware_v_total()
130 if (stream->ctx->dc->caps.vtotal_limited_by_fp2) { in calc_max_hardware_v_total()
131 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h2 * Copyright 2017 Advanced Micro Devices, Inc.
192 #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GEN…
309 #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete…
312 #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete…
315 #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete…
318 #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete…
321 #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete…
324 #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete…
468 …gered when the time(number of refclk cycles) of a programmable number of frames is counted.The cou…
471 …gered when the time(number of refclk cycles) of a programmable number of frames is counted.The cou…
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/linux/drivers/usb/dwc2/
H A Dhcd_ddma.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_ddma.c - DesignWare HS OTG Controller descriptor DMA routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
15 #include <linux/dma-mapping.h>
28 return frame & (FRLISTEN_64_SIZE - 1); in dwc2_frame_list_idx()
35 MAX_DMA_DESC_NUM_GENERIC) - 1); in dwc2_desclist_idx_inc()
40 return (idx - inc) & in dwc2_desclist_idx_dec()
42 MAX_DMA_DESC_NUM_GENERIC) - 1); in dwc2_desclist_idx_dec()
47 return (qh->ep_type == USB_ENDPOINT_XFER_ISOC && in dwc2_max_desc_num()
48 qh->dev_speed == USB_SPEED_HIGH) ? in dwc2_max_desc_num()
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H A Dhcd_intr.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
5 * Copyright (C) 2004-2013 Synopsys, Inc.
15 #include <linux/dma-mapping.h>
35 u16 curr_frame_number = hsotg->frame_number; in dwc2_track_missed_sofs()
36 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1); in dwc2_track_missed_sofs()
43 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { in dwc2_track_missed_sofs()
45 hsotg->frame_num_array[hsotg->frame_num_idx] = in dwc2_track_missed_sofs()
47 hsotg->last_frame_num_array[hsotg->frame_num_idx] = in dwc2_track_missed_sofs()
48 hsotg->last_frame_num; in dwc2_track_missed_sofs()
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H A Dhcd_queue.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
17 #include <linux/dma-mapping.h>
36 * dwc2_periodic_channel_available() - Checks that a channel is available for a
48 * non-periodic transactions in dwc2_periodic_channel_available()
53 num_channels = hsotg->params.host_channels; in dwc2_periodic_channel_available()
54 if ((hsotg->periodic_channels + hsotg->non_periodic_channels < in dwc2_periodic_channel_available()
55 num_channels) && (hsotg->periodic_channels < num_channels - 1)) { in dwc2_periodic_channel_available()
58 dev_dbg(hsotg->dev, in dwc2_periodic_channel_available()
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/linux/drivers/media/usb/uvc/
H A Duvc_video.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * uvc_video.c -- USB Video Class driver - Video handling
5 * Copyright (C) 2005-2010
9 #include <linux/dma-mapping.h>
24 #include <media/v4l2-common.h>
28 /* ------------------------------------------------------------------------
39 pipe = (query & 0x80) ? usb_rcvctrlpipe(dev->udev, 0) in __uvc_query_ctrl()
40 : usb_sndctrlpipe(dev->udev, 0); in __uvc_query_ctrl()
43 return usb_control_msg(dev->udev, pipe, query, type, cs << 8, in __uvc_query_ctrl()
89 * Most controls are little-endian integers, in which case the missing in uvc_query_ctrl()
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/linux/drivers/net/ethernet/cavium/liquidio/
H A Dliquidio_common.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
19 * \brief Common: Structures and macros used in PCI-NIC package by core and
37 u16 micro; member
50 /* pre-defined host->NIC tag values */
60 /* Subcodes are used by host driver/apps to identify the sub-operation
85 #define VF_DRV_REMOVED -1
101 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
123 index = index + count - max; in incr_index()
149 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
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/linux/drivers/net/can/usb/
H A Desd_usb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CAN driver for esd electronics gmbh CAN-USB/2, CAN-USB/3 and CAN-USB/Micro
5 * Copyright (C) 2010-2012 esd electronic system design gmbh, Matthias Fuchs <socketcan@esd.eu>
6 * Copyright (C) 2022-2024 esd electronics gmbh, Frank Jungclaus <frank.jungclaus@esd.eu>
23 MODULE_DESCRIPTION("CAN driver for esd electronics gmbh CAN-USB/2, CAN-USB/3 and CAN-USB/Micro inte…
48 /* esd CAN message flags - dlc field */
54 /* esd CAN message flags - id field */
67 /* bit timing esd CAN-USB */
100 /* Modes for CAN-USB/3, to be used for esd_usb_3_set_baudrate_msg_x.mode */
108 /* Flags for CAN-USB/3, to be used for esd_usb_3_set_baudrate_msg_x.flags */
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/linux/drivers/net/ethernet/amd/
H A Damd8111e.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
4 * Copyright (C) 2004 Advanced Micro Devices
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
73 #include <linux/dma-mapping.h>
87 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
101 void __iomem *mmio = lp->mmio; in amd8111e_read_phy()
114 } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); in amd8111e_read_phy()
122 return -EINVAL; in amd8111e_read_phy()
131 void __iomem *mmio = lp->mmio; in amd8111e_write_phy()
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/linux/Documentation/sound/kernel-api/
H A Dwriting-an-alsa-driver.rst11 Architecture) <http://www.alsa-project.org/>`__ driver. The document
19 low-level driver implementation details. It only describes the standard
26 -------
56 --------------
60 sub-directories contain different modules and are dependent upon the
74 This directory and its sub-directories are for the ALSA sequencer. This
76 as snd-seq-midi, snd-seq-virmidi, etc. They are compiled only when
85 -----------------
88 to be exported to user-space, or included by several files in different
94 -----------------
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h2 * Copyright 2012-2026 Advanced Micro Devices, Inc.
60 * (access to non-DC registers will hang FPGA) */
145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
189 * struct dc_edid_caps - Capabilities read from EDID.
190 * @analog: Whether the monitor is analog. Used by DVI-I handling.
248 Must be zero for wired displays and non-zero for
343 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
416 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
422 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
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/linux/include/linux/
H A Dusb.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/errno.h> /* for -ENODEV */
30 /*-------------------------------------------------------------------------*/
33 * Host-side wrappers for standard USB descriptors ... these are parsed
37 * - devices have one (usually) or more configs;
38 * - configs have one (often) or more interfaces;
39 * - interfaces have one (usually) or more settings;
40 * - each interface setting has zero or (usually) more endpoints.
41 * - a SuperSpeed endpoint has a companion descriptor
45 * Devices may also have class-specific or vendor-specific descriptors.
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/linux/drivers/usb/cdns3/
H A Dcdnsp-mem.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
18 #include "cdnsp-gadget.h"
19 #include "cdnsp-trace.h"
42 seg->trbs = dma_pool_zalloc(pdev->segment_pool, flags, &dma); in cdnsp_segment_alloc()
43 if (!seg->trbs) { in cdnsp_segment_alloc()
49 seg->bounce_buf = kzalloc(max_packet, flags | GFP_DMA); in cdnsp_segment_alloc()
50 if (!seg->bounce_buf) in cdnsp_segment_alloc()
57 seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); in cdnsp_segment_alloc()
59 seg->dma = dma; in cdnsp_segment_alloc()
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