| /linux/Documentation/admin-guide/ |
| H A D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
22 1-1. Terminology
23 1-2. What is cgroup?
25 2-1. Mounting
26 2-2. Organizing Processes and Threads
27 2-2-1. Processes
28 2-2-2. Threads
29 2-3. [Un]populated Notification
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| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
16 * Memory devices
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
23 * Memory Stick
25 A printed circuit board that aggregates multiple memory devices in
28 called DIMM (Dual Inline Memory Module).
30 * Memory Socket
32 A physical connector on the motherboard that accepts a single memory
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| /linux/include/linux/mux/ |
| H A D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mux/driver.h - definitions for the multiplexer driver interface
13 #include <dt-bindings/mux/mux.h>
22 * struct mux_control_ops - Mux controller operations for a mux chip.
30 * struct mux_control - Represents a mux controller.
33 * @cached_state: The current mux controller state, or -1 if none.
57 * struct mux_chip - Represents a chip holding mux controllers.
58 * @controllers: Number of mux controllers handled by the chip.
62 * @mux: Array of mux controllers that are handled.
65 unsigned int controllers; member
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | renesas,dbsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas DDR Bus Controllers
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 Renesas SoCs contain one or more memory controllers. These memory
14 controllers differ from one SoC variant to another, and are called by
21 - renesas,dbsc-r8a73a4 # R-Mobile APE6
22 - renesas,dbsc3-r8a7740 # R-Mobile A1
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| H A D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
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| H A D | st,stm32mp25-omm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STM32 Octo Memory Manager (OMM)
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 The STM32 Octo Memory Manager is a low-level interface that enables an
17 - Two single/dual/quad/octal SPI interfaces
18 - Two ports for pin assignment
22 const: st,stm32mp25-omm
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| H A D | xlnx,versal-net-ddrmc5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal NET Memory Controller
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
13 The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5
14 compact and extended memory interfaces. Versal NET DDR memory controller
17 MMCM (Mixed-Mode Clock Manager) errors and General software errors.
21 const: xlnx,versal-net-ddrmc5
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| H A D | xlnx,versal-ddrmc-edac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
20 const: xlnx,versal-ddrmc
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| /linux/drivers/edac/ |
| H A D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
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| H A D | skx_common.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
55 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
56 * memory errors should fit one of these masks:
67 * Errors from either the memory of the 1-level memory system or the
68 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
72 * Errors from the 1st level memory (the fast "near" memory as cache)
73 * of the 2-level memory system.
77 /* Max RRL register sets per {,sub-,pseudo-}channel. */
96 /* RRL registers per {,sub-,pseudo-}channel. */
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| /linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
26 io-width:
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| /linux/Documentation/devicetree/bindings/mips/brcm/ |
| H A D | soc.txt | 5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
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| /linux/Documentation/arch/xtensa/ |
| H A D | atomctl.rst | 10 can do Atomic Transactions to the memory internally.
12 2. With and without An Intelligent Memory Controller which
19 On the FPGA Cards we typically simulate an Intelligent Memory controller
21 Memory controller we let it to the atomic operations internally while
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, though non-MX controllers likely
29 CUSTOMER-WARNING:
30 Virtually all customers buy their memory controllers from vendors that
31 don't support atomic RCW memory transactions and will likely want to
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| /linux/Documentation/devicetree/bindings/arm/bcm/ |
| H A D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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| /linux/drivers/scsi/aic7xxx/ |
| H A D | aic7xxx_osm_pci.c | 2 * Linux driver attachment glue for PCI based controllers.
4 * Copyright (c) 2000-2001 Adaptec Inc.
18 * 3. Neither the names of the above-listed copyright holders nor the names
50 /* aic7850 based controllers */
52 /* aic7860 based controllers */
58 /* aic7870 based controllers */
65 /* aic7880 based controllers */
75 /* aic7890 based controllers */
83 /* aic7890 based controllers */
91 /* aic7892 based controllers */
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| /linux/Documentation/core-api/ |
| H A D | debugging-via-ohci1394.rst | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
8 Basically all FireWire controllers which are in use today are compliant
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
16 physical system memory and, for read requests, send the result of
17 the physical memory read back to the requester.
19 With that, it is possible to debug issues by reading interesting memory
22 Retrieving a full system memory dump is also possible over the FireWire,
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| /linux/drivers/scsi/megaraid/ |
| H A D | megaraid_mbox.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (c) 2003-2004 LSI Logic Corporation.
94 #define MBOX_MAX_SG_SIZE 32 // maximum scatter-gather list size
102 #define MBOX_SYNC_DELAY_200 200 // 200 micro-seconds
112 * mbox_ccb_t - command control block specific to mailbox based controllers
117 * @sgl64 : 64-bit scatter-gather list
118 * @sgl32 : 32-bit scatter-gather list
119 * @sgl_dma_h : dma handle for the scatter-gather list
126 * command control block specific to the mailbox based controllers
145 * mraid_device_t - adapter soft state structure for mailbox controllers
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | st,stm32mp25-ospi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 - $ref: spi-controller.yaml#
17 const: st,stm32mp25-ospi
22 memory-region:
24 Memory region to be used for memory-map read access.
25 In memory-mapped mode, read access are performed from the memory
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| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | srf-metrics.json | 4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
25 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
32 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
46 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
53 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
110 …oller (IIO) of IO reads that are initiated by end device controllers that are requesting memory fr…
116 …roller (IIO) of IO writes that are initiated by end device controllers that are writing memory to …
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| /linux/Documentation/devicetree/bindings/memory-controllers/ti/ |
| H A D | emif.txt | 1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
6 of the EMIF IP and memory parts attached to it. Certain revisions
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
12 is the IP revision of the specific EMIF instance. For newer controllers,
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
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| /linux/drivers/net/can/sja1000/ |
| H A D | ems_pcmcia.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010 Markus Plessing <plessing@ems-wuensche.com>
22 MODULE_AUTHOR("Markus Plessing <plessing@ems-wuensche.com>");
23 MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-CARD cards");
43 * This means normal output mode , push-pull and the correct polarity.
54 #define EMS_PCMCIA_MEM_SIZE 4096 /* Size of the remapped io-memory */
55 #define EMS_PCMCIA_CAN_BASE_OFFSET 0x100 /* Offset where controllers starts */
56 #define EMS_PCMCIA_CAN_CTRL_SIZE 0x80 /* Memory size for each controller */
59 #define EMS_CMD_MAP 0x03 /* Map CAN controllers into card' memory */
60 #define EMS_CMD_UMAP 0x02 /* Unmap CAN controllers from card' memory */
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
18 presenting a set of fixed windows describing a subset of IO, Memory and
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
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| /linux/Documentation/gpu/ |
| H A D | tegra.rst | 11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
56 --------------------------
58 .. kernel-doc:: drivers/gpu/host1x/syncpt.c
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| /linux/drivers/irqchip/ |
| H A D | irq-versatile-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Versatile FPGA-based IRQ controllers
35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
36 * @base: memory offset in virtual memory
48 /* we cannot allocate memory when the controllers are initially registered */
55 u32 mask = 1 << d->hwirq; in fpga_irq_mask()
57 writel(mask, f->base + IRQ_ENABLE_CLEAR); in fpga_irq_mask()
63 u32 mask = 1 << d->hwirq; in fpga_irq_unmask()
65 writel(mask, f->base + IRQ_ENABLE_SET); in fpga_irq_unmask()
72 seq_puts(p, irq_domain_get_of_node(f->domain)->name); in fpga_irq_print_chip()
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| /linux/Documentation/nvme/ |
| H A D | nvme-pci-endpoint-target.rst | 1 .. SPDX-License-Identifier: GPL-2.0
51 data buffer is transferred from the host into a local memory buffer before
53 memory buffer is allocated to execute the command and the content of that
57 -----------------------
73 4) The boot partition support (BPS), Persistent Memory Region Supported (PMRS)
74 and Controller Memory Buffer Supported (CMBS) capabilities are never
78 ------------------
86 with excessive local memory usage for executing commands, MDTS defaults to 512
90 ------------------------------------------------------
92 Most PCI endpoint controllers provide a limited number of mapping windows for
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