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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Darm,pl353-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
14 The PL353 Static Memory Controller is a bus where you can connect two kinds
15 of memory interfaces, which are NAND and memory mapped interfaces (such as
23 const: arm,pl353-smc-r2p1
[all …]
H A Drenesas,dbsc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas DDR Bus Controllers
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 Renesas SoCs contain one or more memory controllers. These memory
14 controllers differ from one SoC variant to another, and are called by
21 - renesas,dbsc-r8a73a4 # R-Mobile APE6
22 - renesas,dbsc3-r8a7740 # R-Mobile A1
[all …]
H A Darm,pl35x-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
[all …]
H A Dbrcm,brcmstb-memc-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Memory controller (MEMC) for Broadcom STB
10 - Florian Fainelli <f.fainelli@gmail.com>
15 - description: Revision > 2.1 controllers
17 - enum:
18 - brcm,brcmstb-memc-ddr-rev-b.2.2
19 - brcm,brcmstb-memc-ddr-rev-b.2.3
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H A Dst,stm32mp25-omm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STM32 Octo Memory Manager (OMM)
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 The STM32 Octo Memory Manager is a low-level interface that enables an
17 - Two single/dual/quad/octal SPI interfaces
18 - Two ports for pin assignment
22 const: st,stm32mp25-omm
[all …]
H A Dsynopsys,ddrc-ecc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys IntelliDDR Multi Protocol memory controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Manish Narani <manish.narani@xilinx.com>
12 - Michal Simek <michal.simek@xilinx.com>
15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
16 32-bit bus width configurations.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
26 io-width:
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/freebsd/sys/contrib/device-tree/Bindings/mips/brcm/
H A Dsoc.txt5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
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/freebsd/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dgpmc-eth.txt3 Besides being used to interface with external memory devices, the
4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
5 such as ethernet controllers to processors using the TI GPMC as a data bus.
7 Ethernet controllers connected to TI GPMC are represented as child nodes of
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
[all …]
/titanic_52/usr/src/man/man3rsm/
H A Drsm_get_interconnect_topology.3rsm8 rsm_get_interconnect_topology, rsm_free_interconnect_topology \- get or free
13 cc [ \fIflag\fR... ] \fIfile\fR... -lrsm [ \fIlibrary\fR... ]
36 memory can thus find the set of existing local controllers and correctly assign
37 controllers for the creation and publishing of segments. Exported segments may
38 also be efficiently distributed over the set of controllers consistent with the
40 is to import memory must be informed of the segment id(s) and controller(s)
41 used in the exporting of memory, this needs to be done using some out-of-ban
[all...]
/freebsd/share/man/man4/
H A Dsym.43 .\" PCI SCSI controllers.
5 .\" Copyright (C) 1999-2000 Gerard Roudier <groudier@club-internet.fr>
12 .\" This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13 .\" Copyright (C) 1998-1999 Gerard Roudier
16 .\" a port of the FreeBSD ncr driver to Linux-1.2.13.
20 .\" Stefan Esser <se@mi.Uni-Koeln.de>
24 .\" FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
32 .\" ----------------------------------------------------------------------------
67 .Bd -ragged -offset indent
82 .Bd -literal -offset indent
[all …]
H A Dahc.42 .\" SPDX-License-Identifier: BSD-3-Clause
39 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
66 .Tn SCSI-Select
74 For systems that store non-volatile settings in a system specific manner
80 many chip-down motherboard configurations.
90 .Bd -ragged -offset indent
91 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
108 .Bl -enum -compact
110 Multiplexed Twin Channel Device - One controller servicing two busses.
[all …]
H A Dagp.444 .Bl -tag -width "NVIDIA:" -compact
54 i810, i810-DC100, i810E, i815, 830M, 845G, 845M, 852GM, 852GME, 855GM, 855GME, 865G, 915G and 915GM…
58 nForce and nForce2 AGP controllers
68 .Xr X 7 Pq Pa ports/x11/xorg-docs
69 on the Intel i81x controllers.
77 .Bl -tag -width indent
83 .Bd -literal
102 This does not unbind or free any allocated memory, which is the
109 .Bd -literal
118 Allocate physical memory suitable for mapping into the AGP aperture.
[all …]
H A Dimcsmb.42 .\" SPDX-License-Identifier: BSD-2-Clause
31 .Nd Intel integrated Memory Controller (iMC) SMBus controller driver
40 .Bd -literal -offset indent
48 support for the SMBus controller functionality in the integrated Memory
49 Controllers (iMCs) embedded in Intel Sandybridge-Xeon, Ivybridge-Xeon,
50 Haswell-Xeon, and Broadwell-Xeon CPUs.
52 each iMC implements two SMBus controllers (iMC-SMBs).
53 The iMC-SMBs are used by the iMCs to read configuration information from the
58 The iMC-SMBs are
60 general-purpose SMBus controllers.
[all …]
H A Dsis.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
56 controllers based on the Silicon Integrated Systems SiS 900
63 The SiS 900 is a 100Mbps Ethernet MAC and MII-compliant transceiver
70 The SiS 900 and SiS 7016 both have a 128-bit multicast hash filter
81 .Bl -tag -width 10baseTXUTP
93 .Sq full-duplex
95 .Sq half-duplex
103 .Sq full-duplex
[all …]
/titanic_52/usr/src/uts/sun4u/sys/
H A Dmc.h37 * Interface of Memory Controller driver
39 * Logical view: memory -> segment -> bank -> device group -> device
40 * physical view: mc -> device group -> device
50 * its upper layer. For instance, one memory module group has N memory module
[all...]
/freebsd/sys/dev/imcsmb/
H A Dimcsmb_pci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2017-2018 Panasas
52 /* (Sandy,Ivy)bridge-Xeon and (Has,Broad)well-Xeon CPUs contain one or two
53 * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate
54 * SMBus controllers. These are used for reading SPD data from the DIMMs, and
55 * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
57 * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs.
59 * The publicly available documentation for the iMC SMBus controllers can be
60 * found in the CPU datasheets for (Sandy,Ivy)bridge-Xeon and
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Daspeed-smc.txt1 * Aspeed Firmware Memory controller
2 * Aspeed SPI Flash Memory Controller
4 The Firmware Memory Controller in the Aspeed AST2500 SoC supports
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
[all …]
/titanic_52/usr/src/lib/libdiskmgt/common/
H A Dlibdiskmgt.h44 * disks, controllers, and related components.
48 * -------
62 * --
[all...]
/titanic_52/usr/src/man/man1m/
H A Dnvmeadm.1m34 .Cm get-logpage
39 .Cm get-features
41 .Op Ar feature-list
46 .Op Ar lba-format
49 .Cm secure-erase
63 utility can be used to enumerate the NVMe controllers and their
65 namespace, and to format or secure-erase a NVMe controller or
70 in a human-readable form were applicable.
71 Generally all 0-based counts are normalized and values may be
72 converted to human-readabl
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dadi,axi-dmac.txt1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
[all …]
/freebsd/sys/i386/conf/
H A DGENERIC2 # GENERIC -- Generic kernel configuration file for FreeBSD/i386
7 # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
27 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
44 options UFS_GJOURNAL # Enable gjournal-based UFS journaling
54 options PSEUDOFS # Pseudo-filesystem framework
55 options TMPFS # Efficient memory filesystem
71 options SYSVSHM # SYSV-style shared memory
72 options SYSVMSG # SYSV-style message queues
73 options SYSVSEM # SYSV-style semaphores
74 options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
[all …]
/freebsd/sys/amd64/conf/
H A DGENERIC2 # GENERIC -- Generic kernel configuration file for FreeBSD/amd64
7 # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
23 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
27 options NUMA # Non-Uniform Memory Architecture support
47 options UFS_GJOURNAL # Enable gjournal-based UFS journaling
57 options PSEUDOFS # Pseudo-filesystem framework
58 options TMPFS # Efficient memory filesystem
76 options SYSVSHM # SYSV-style shared memory
77 options SYSVMSG # SYSV-style message queues
78 options SYSVSEM # SYSV-style semaphores
[all …]
/freebsd/sys/powerpc/conf/
H A DGENERIC2 # GENERIC -- Generic kernel configuration file for FreeBSD/powerpc
7 # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
25 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
32 options PSERIES # PAPR-compliant systems
48 options UFS_GJOURNAL # Enable gjournal-based UFS journaling
58 options PSEUDOFS # Pseudo-filesystem framework
59 options TMPFS # Efficient memory filesystem
74 options SYSVSHM # SYSV-style shared memory
[all...]

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