| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | ste-dma40.txt | 4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
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| H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsso
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| H A D | ti-edma.txt | 8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
21 - reg-names: "edma3_cc"
22 - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
23 - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
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| H A D | qcom_hidma_mgmt.txt | 4 memcpy and memset capabilities. It has been designed for virtualized
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
9 among channels based on the priority and weight assignments.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
22 occupy the bus for in a single transaction. A memcpy requested is
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
27 occupy the bus for in a single transaction. A memcpy request is
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| H A D | arm-pl08x.txt | 4 - compatible: "arm,pl080", "arm,primecell";
7 - arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
11 - reg: Address range of the PL08x registers
12 - interrupt: The PL08x interrupt number
13 - clocks: The clock running the IP core clock
14 - clock-names: Must contain "apb_pclk"
15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
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| H A D | lpc1850-dmamux.txt | 4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
15 - dma-requests: Number of DMA requests the controller can handle
20 compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
21 arm,primecell-periphid = <0x00041080>;
25 clock-names = "apb_pclk";
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| H A D | ti-dma-crossbar.txt | 4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
13 - dma-requests: Number of DMA requests the controller can handle
16 - ti,dma-safe-map: Safe routing value for unused request lines
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
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| /freebsd/contrib/libsamplerate/ |
| H A D | src_zoh.c | 2 ** Copyright (c) 2002-2021, Erik de Castro Lopo <erikd@mega-nerd.com>
5 ** This code is released under 2-clause BSD license. Please see the
48 /*----------------------------------------------------------------------------------------
57 if (data->input_frames <= 0) in zoh_vari_process()
60 if (state->private_data == NULL) in zoh_vari_process()
63 priv = (ZOH_DATA*) state->private_data ; in zoh_vari_process()
65 if (!priv->dirty) in zoh_vari_process()
67 for (ch = 0 ; ch < state->channels ; ch++) in zoh_vari_process()
68 priv->last_value [ch] = data->data_in [ch] ; in zoh_vari_process()
69 priv->dirty = true ; in zoh_vari_process()
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| H A D | src_linear.c | 2 ** Copyright (c) 2002-2021, Erik de Castro Lopo <erikd@mega-nerd.com>
5 ** This code is released under 2-clause BSD license. Please see the
50 /*----------------------------------------------------------------------------------------
59 if (data->input_frames <= 0) in linear_vari_process()
62 if (state->private_data == NULL) in linear_vari_process()
65 priv = (LINEAR_DATA*) state->private_data ; in linear_vari_process()
67 if (!priv->dirty) in linear_vari_process()
69 for (ch = 0 ; ch < state->channels ; ch++) in linear_vari_process()
70 priv->last_value [ch] = data->data_in [ch] ; in linear_vari_process()
71 priv->dirty = true ; in linear_vari_process()
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| H A D | src_sinc.c | 2 ** Copyright (c) 2002-2021, Erik de Castro Lopo <erikd@mega-nerd.com>
5 ** This code is released under 2-clause BSD license. Please see the
44 typedef int _CHECK_SHIFT_BITS[2 * (SHIFT_BITS < sizeof (increment_t) * 8 - 1) - 1]; /* sanity check…
70 /* Sure hope noone does more than 128 channels at once. */
82 static SRC_ERROR prepare_data (SINC_FILTER *filter, int channels, SRC_DATA *data, int half_filter_c…
150 { return ((x) & ((((increment_t) 1) << SHIFT_BITS) - 1)) ; in fp_fraction_part()
161 return (divident + (divisor - 1)) / divisor ; in int_div_ceil()
164 /*----------------------------------------------------------------------------------------
209 sinc_filter_new (int converter_type, int channels) in sinc_filter_new() argument
214 assert (channels > 0 && channels <= MAX_CHANNELS) ; in sinc_filter_new()
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| /freebsd/share/examples/sound/ |
| H A D | simple.c | 2 * SPDX-License-Identifier: BSD-2-Clause
35 * Split input buffer into channels. The input buffer is in interleaved format,
36 * which means if we have 2 channels (L and R), this is what the buffer of 8
43 uint8_t *in = config->buf; in to_channels()
48 for (byte = 0; byte < config->buffer_info.bytes; in to_channels()
49 byte += config->sample_size) { in to_channels()
54 i = byte / config->sample_size; in to_channels()
57 channel = i % config->audio_info.max_channels; in to_channels()
60 offset = i / config->audio_info.max_channels; in to_channels()
63 index = (channel * config->chsamples + offset) * in to_channels()
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| /freebsd/sys/contrib/dev/iwlwifi/mld/ |
| H A D | scan.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2024-2025 Intel Corporation
7 #include "iwl-utils.h"
35 /* adaptive dwell default APs number for P2P social channels (1, 6, 11) */
38 /* adaptive dwell number of APs override for P2P friendly GO channels */
41 /* adaptive dwell number of APs override for P2P social channels */
47 /* adaptive dwell number of APs override mask for social channels */
52 /* minimal number of 2GHz and 5GHz channels in the regular scan request */
98 struct ieee80211_channel **channels; member
130 if (vif == data->current_vif) in iwl_mld_scan_respect_p2p_go_iter()
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| /freebsd/sys/contrib/dev/iwlwifi/mvm/ |
| H A D | scan.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
13 #include "iwl-io.h"
14 #include "iwl-utils.h"
33 /* adaptive dwell default APs number in social channels (1, 6, 11) */
35 /* number of scan channels */
39 /* adaptive dwell number of APs override mask for social channels */
41 /* adaptive dwell number of APs override for p2p friendly GO channels */
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| H A D | nvm.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2019, 2021-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 #include "iwl-trans.h"
12 #include "iwl-csr.h"
14 #include "iwl-nvm-utils.h"
15 #include "iwl-nvm-parse.h"
16 #include "iwl-prph.h"
62 nvm_resp = (void *)pkt->data; in iwl_nvm_write_chunk()
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| /freebsd/usr.sbin/virtual_oss/virtual_oss/ |
| H A D | virtual_oss.c | 1 /*-
2 * Copyright (c) 2012-2022 Hans Petter Selasky
70 usleep((delay - (nsec % delay)) / 1000); in virtual_oss_wait()
91 pvc->sync_busy = 1; in vclient_read_linear()
97 total -= read; in vclient_read_linear()
99 if (!pvc->profile->synchronized || pvc->sync_wakeup || in vclient_read_linear()
108 pvc->sync_busy = 0; in vclient_read_linear()
109 if (pvc->sync_wakeup) in vclient_read_linear()
112 vclient_tx_equalizer(pvc, dst - total_read, total_read); in vclient_read_linear()
125 pvc->sync_busy = 1; in vclient_write_linear()
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| /freebsd/contrib/wpa/src/drivers/ |
| H A D | driver_hostap.c | 3 * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
71 fc = le_to_host16(hdr->frame_control); in handle_data()
78 sa = hdr->addr2; in handle_data()
82 wpa_supplicant_event(drv->hapd, EVENT_RX_FROM_UNKNOWN, &event); in handle_data()
85 left = len - sizeof(*hdr); in handle_data()
97 left -= sizeof(rfc1042_header); in handle_data()
106 left -= 2; in handle_data()
109 drv_event_eapol_rx(drv->hapd, sa, pos, left); in handle_data()
127 fc = le_to_host16(hdr->frame_control); in handle_tx_callback()
132 event.tx_status.dst = hdr->addr1; in handle_tx_callback()
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| /freebsd/usr.sbin/bhyve/ |
| H A D | audio.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
65 * audio_init - initialize an instance of audio player
66 * @dev_name - the backend sound device used to play / capture
67 * @dir - dir = 1 for write mode, dir = 0 for read mode
92 if (nlen < sizeof(aud->dev_name)) in audio_init()
93 memcpy(aud->dev_name, dev_name, nlen + 1); in audio_init()
100 aud->dir = dir; in audio_init()
102 aud->fd = open(aud->dev_name, aud->dir ? O_WRONLY : O_RDONLY, 0); in audio_init()
103 if (aud->fd == -1) { in audio_init()
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| /freebsd/sys/net80211/ |
| H A D | ieee80211_regdomain.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2005-2008 Sam Leffler, Errno Consulting
53 if (maxchan > ic->ic_nchans) in null_getradiocaps()
54 maxchan = ic->ic_nchans; in null_getradiocaps()
55 memcpy(c, ic->ic_channels, maxchan*sizeof(struct ieee80211_channel)); in null_getradiocaps()
70 if (ic->ic_regdomain.regdomain == 0 && in ieee80211_regdomain_attach()
71 ic->ic_regdomain.country == CTRY_DEFAULT) { in ieee80211_regdomain_attach()
72 ic->ic_regdomain.location = ' '; /* both */ in ieee80211_regdomain_attach()
75 ic->ic_getradiocaps = null_getradiocaps; in ieee80211_regdomain_attach()
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| H A D | ieee80211_scan_sta.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
99 (((const uint8_t *)(addr))[IEEE80211_ADDR_LEN - 1] % STA_HASHSIZE)
112 /* ap-related state */
119 * for use. If non-zero the entry was deemed not suitable and it's
174 TAILQ_INIT(&st->st_entry); in sta_attach()
175 ss->ss_priv = st; in sta_attach()
186 struct sta_table *st = ss->ss_priv; in sta_detach()
194 nrefs--; /* NB: we assume caller locking */ in sta_detach()
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| /freebsd/share/man/man4/ |
| H A D | xdma.4 | 5 .\" Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
38 .Bd -ragged -offset indent
42 To compile xDMA FDT-based test driver, place the following line as well:
43 .Bd -literal -offset indent
54 device provides a virtual DMA controller and virtual channels called xchans.
55 The controller provides virtual channels management (allocation, deallocation,
60 .Bl -hang -offset indent -width xxxxxxxx
62 A non-stop periodic transfer designed for applications like audio.
63 .It Nm Memcpy
64 A memory-to-memory transfer.
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| /freebsd/sys/contrib/dev/mediatek/mt76/ |
| H A D | mt76_connac_mcu.c | 1 // SPDX-License-Identifier: ISC
107 struct mt76_dev *dev = phy->dev; in mt76_connac_mcu_set_channel_domain()
111 n_max_channels = phy->sband_2g.sband.n_channels + in mt76_connac_mcu_set_channel_domain()
112 phy->sband_5g.sband.n_channels + in mt76_connac_mcu_set_channel_domain()
113 phy->sband_6g.sband.n_channels; in mt76_connac_mcu_set_channel_domain()
118 return -ENOMEM; in mt76_connac_mcu_set_channel_domain()
122 for (i = 0; i < phy->sband_2g.sband.n_channels; i++) { in mt76_connac_mcu_set_channel_domain()
123 chan = &phy->sband_2g.sband.channels[i]; in mt76_connac_mcu_set_channel_domain()
124 if (chan->flags & IEEE80211_CHAN_DISABLED) in mt76_connac_mcu_set_channel_domain()
127 channel.hw_value = cpu_to_le16(chan->hw_value); in mt76_connac_mcu_set_channel_domain()
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| /freebsd/sys/contrib/dev/iwlwifi/ |
| H A D | iwl-eeprom-parse.c | |
| /freebsd/sys/contrib/dev/athk/ath10k/ |
| H A D | wow.c | 1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2015-2017 Qualcomm Atheros, Inc.
14 #include "wmi-ops.h"
26 struct ath10k *ar = arvif->ar; in ath10k_wow_vif_cleanup()
30 ret = ath10k_wmi_wow_add_wakeup_event(ar, arvif->vdev_id, i, 0); in ath10k_wow_vif_cleanup()
33 wow_wakeup_event(i), arvif->vdev_id, ret); in ath10k_wow_vif_cleanup()
38 for (i = 0; i < ar->wow.max_num_patterns; i++) { in ath10k_wow_vif_cleanup()
39 ret = ath10k_wmi_wow_del_pattern(ar, arvif->vdev_id, i); in ath10k_wow_vif_cleanup()
42 i, arvif->vdev_id, ret); in ath10k_wow_vif_cleanup()
55 lockdep_assert_held(&ar->conf_mutex); in ath10k_wow_cleanup()
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| /freebsd/lib/virtual_oss/bt/ |
| H A D | bt.c | 1 /*-
2 * Copyright (c) 2015-2019 Hans Petter Selasky
62 struct sbc_header *phdr = (struct sbc_header *)cfg->mtu_data; in bt_receive()
63 struct sbc_encode *sbc = cfg->handle.sbc_enc; in bt_receive()
73 switch (cfg->blocks) { in bt_receive()
75 sbc->blocks = 4; in bt_receive()
78 sbc->blocks = 8; in bt_receive()
81 sbc->blocks = 12; in bt_receive()
84 sbc->blocks = 16; in bt_receive()
88 switch (cfg->bands) { in bt_receive()
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| /freebsd/usr.sbin/virtual_oss/virtual_equalizer/ |
| H A D | equalizer.c | 1 /*-
55 /* (block_size * 2) elements, half-complex, freq domain */
77 * Masking window value for -1 < x < 1.
105 e->do_normalize = 1; in equalizer_load_freq_amps()
107 e->do_normalize = 0; in equalizer_load_freq_amps()
110 for (i = 0; i <= (e->block_size / 2); ++i) { in equalizer_load_freq_amps()
111 const double f = (i * e->rate) / e->block_size; in equalizer_load_freq_amps()
118 next_f = e->rate; in equalizer_load_freq_amps()
137 e->fftw_freq[i] = ((f - prev_f) / (next_f - prev_f)) * (next_amp - prev_amp) + prev_amp; in equalizer_load_freq_amps()
147 e->rate = rate; in equalizer_init()
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