Home
last modified time | relevance | path

Searched +full:memcpy +full:- +full:burst +full:- +full:size (Results 1 – 25 of 162) sorted by relevance

1234567

/linux/Documentation/devicetree/bindings/dma/
H A Darm-pl08x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: dma-controller.yaml#
22 - arm,pl080
23 - arm,pl081
25 - compatible
[all …]
/linux/drivers/dma/
H A Damba-pl08x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
36 * On burst request from peripheral
37 * Destination burst from DMAC to peripheral
38 * Clear burst request
[all …]
H A Dnbpfaxi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
10 #include <linux/dma-mapping.h>
22 #include <dt-bindings/dma/nbpfaxi.h>
61 #define NBPF_CHAN_CFG_SDS 0xf000 /* Source Data Size: 0: 8 bits,... , 7: 1024 bits */
62 #define NBPF_CHAN_CFG_DDS 0xf0000 /* Destination Data Size: as above */
104 * 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
108 * allocated from coherent memory - one per SG segment
115 * Therefore for both cases (a) and (b) at run-time objects (2) and (3) shall be
142 * struct nbpf_desc - DMA transfer descriptor
[all …]
H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
59 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
[all …]
H A Dste_dma40.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Maximum size for a single dma descriptor
8 * Size is limited to 16 bits.
9 * Size is in the units of addr-widths (1,2,4,8 bytes)
14 /* dev types for memcpy */
15 #define STEDMA40_DEV_DST_MEMORY (-1)
16 #define STEDMA40_DEV_SRC_MEMORY (-1)
38 /* The value 4 indicates that PEN-reg shall be set to 0 */
63 * struct stedma40_half_channel_info - dst/src channel configuration
67 * @p_size: Burst size
[all …]
H A Dpl330.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/dma-mapping.h>
46 CCTRL6, /* Cacheable write-through, allocate on writes only */
47 CCTRL7, /* Cacheable write-back, allocate on writes only */
245 * at 1byte/burst for P<->M and M<->M respectively.
246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247 * should be enough for P<->M and M<->M respectively.
303 * and burst size/length are assumed same.
324 /* Size to xfer */
351 BURST, enumerator
[all …]
/linux/net/netfilter/
H A Dxt_hashlimit.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * xt_hashlimit - Netfilter module to limit the number of packets per time
6 * (C) 2003-2004 by Harald Welte <laforge@netfilter.org>
7 * (C) 2006-2012 Patrick McHardy <kaber@trash.net>
8 * Copyright © CC Computer Consultants GmbH, 2007 - 2008
49 MODULE_DESCRIPTION("Xtables: per hash-bucket rate-limit match");
89 /* static / read-only parts in the beginning */
108 int64_t burst; member
143 to->mode = cfg->mode; in cfg_copy()
144 to->avg = cfg->avg; in cfg_copy()
[all …]
/linux/include/linux/amba/
H A Dpl08x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
6 * Copyright (C) 2010 ST-Ericsson SA
32 * struct pl08x_channel_data - data structure to pass info between
48 * can be the address of a FIFO register for burst requests for example.
84 * struct pl08x_platform_data - the platform configuration for the PL08x
91 * @memcpy_burst_size: the appropriate burst size for memcpy operations
93 * @memcpy_prot_buff: whether memcpy DMA is bufferable
94 * @memcpy_prot_cache: whether memcpy DMA is cacheable
/linux/Documentation/driver-api/dmaengine/
H A Dprovider.rst20 DMA-eligible devices to the controller itself. Whenever the device
25 parameter: the transfer size. At each clock cycle, it would transfer a
26 byte of data from one buffer to another, until the transfer size has
42 using a parameter called the burst size, that defines how many single
44 transfer into smaller sub-transfers.
49 non-contiguous buffers to a contiguous buffer, which is called
50 scatter-gather.
53 scatter-gather. So we're left with two cases here: either we have a
56 that implements in hardware scatter-gather.
72 not and the three parameters we saw earlier: the burst size, the
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dcn10k.c1 // SPDX-License-Identifier: GPL-2.0
30 if (!test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) { in otx2_init_hw_ops()
31 pfvf->hw_ops = &otx2_hw_ops; in otx2_init_hw_ops()
35 pfvf->hw_ops = &cn10k_hw_ops; in otx2_init_hw_ops()
46 if (!test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) in cn10k_lmtst_init()
49 /* Total LMTLINES = num_online_cpus() * 32 (For Burst flush).*/ in cn10k_lmtst_init()
50 pfvf->tot_lmt_lines = (num_online_cpus() * LMT_BURST_SIZE); in cn10k_lmtst_init()
51 pfvf->hw.lmt_info = alloc_percpu(struct otx2_lmt_info); in cn10k_lmtst_init()
53 mutex_lock(&pfvf->mbox.lock); in cn10k_lmtst_init()
54 req = otx2_mbox_alloc_msg_lmtst_tbl_setup(&pfvf->mbox); in cn10k_lmtst_init()
[all …]
H A Dotx2_tc.c1 // SPDX-License-Identifier: GPL-2.0
32 #define MCAST_INVALID_GRP (-1U)
54 u32 burst; member
58 static void otx2_get_egress_burst_cfg(struct otx2_nic *nic, u32 burst, in otx2_get_egress_burst_cfg() argument
64 if (is_dev_otx2(nic->pdev)) { in otx2_get_egress_burst_cfg()
72 /* Burst is calculated as in otx2_get_egress_burst_cfg()
74 * Max supported burst size is 130,816 bytes. in otx2_get_egress_burst_cfg()
76 burst = min_t(u32, burst, max_burst); in otx2_get_egress_burst_cfg()
77 if (burst) { in otx2_get_egress_burst_cfg()
78 *burst_exp = ilog2(burst) ? ilog2(burst) - 1 : 0; in otx2_get_egress_burst_cfg()
[all …]
/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
29 #include "../virt-dma.h"
71 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
101 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
102 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
103 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
104 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
105 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
115 * fail. Today davinci-pcm is the only user of this driver and
[all …]
/linux/drivers/net/wireless/ti/wlcore/
H A Dboot.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2010 Nokia Corporation
44 strscpy(wl->chip.fw_ver_str, static_data->fw_version, in wlcore_boot_parse_fw_ver()
45 sizeof(wl->chip.fw_ver_str)); in wlcore_boot_parse_fw_ver()
47 ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u", in wlcore_boot_parse_fw_ver()
48 &wl->chip.fw_ver[0], &wl->chip.fw_ver[1], in wlcore_boot_parse_fw_ver()
49 &wl->chip.fw_ver[2], &wl->chip.fw_ver[3], in wlcore_boot_parse_fw_ver()
50 &wl->chip.fw_ver[4]); in wlcore_boot_parse_fw_ver()
54 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver)); in wlcore_boot_parse_fw_ver()
55 ret = -EINVAL; in wlcore_boot_parse_fw_ver()
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
22 #include "dw-hdma-v0-core.h"
24 #include "../virt-dma.h"
35 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
37 if (chip->ops->pci_address) in dw_edma_get_pci_address()
38 return chip->ops->pci_address(chip->dev, cpu_addr); in dw_edma_get_pci_address()
[all …]
/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_acl.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2020-2021 Marvell International Ltd. All rights reserved. */
22 #define rule_match_set_n(match_p, type, val_p, size) \ argument
23 memcpy(&(match_p)[PRESTERA_ACL_RULE_MATCH_TYPE_##type], \
24 val_p, size)
26 memcpy(&(match_p)[PRESTERA_ACL_RULE_MATCH_TYPE_##type], \
117 u64 burst; member
/linux/drivers/scsi/qla2xxx/
H A Dqla_sup.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
18 * qla2x00_lock_nvram_access() -
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_lock_nvram_access()
28 data = rd_reg_word(&reg->nvram); in qla2x00_lock_nvram_access()
31 data = rd_reg_word(&reg->nvram); in qla2x00_lock_nvram_access()
35 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
36 rd_reg_word(&reg->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
38 data = rd_reg_word(&reg->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
42 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
[all …]
/linux/drivers/media/dvb-frontends/
H A Dcx24116.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Conexant cx24116/cx24118 - DVBS/S2 Satellite demod/tuner driver
5 Copyright (C) 2006-2008 Steven Toth <stoth@hauppauge.com>
6 Copyright (C) 2006-2007 Georg Acher
7 Copyright (C) 2007-2008 Darron Broad
45 #define CX24116_DEFAULT_FIRMWARE "dvb-fe-cx24116.fw"
74 /* Select DVB-S demodulator, else DVB-S2 */
81 /* arg buffer size */
115 /* DiSEqC burst */
119 /* DiSEqC tone burst */
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm6846.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm63178.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6878.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6855.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm6856.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
[all …]
/linux/drivers/bus/
H A Dimx-weim.c19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
78 { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
80 { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
82 { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
83 { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
85 { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
92 struct device_node *np = pdev->dev.of_node; in imx_weim_gpr_setup()
107 gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr"); in imx_weim_gpr_setup()
109 dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n"); in imx_weim_gpr_setup()
118 val = (range.size / SZ_32M) | 1; in imx_weim_gpr_setup()
[all …]
/linux/drivers/infiniband/sw/siw/
H A Dsiw_qp_tx.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
4 /* Copyright (c) 2008-2019, IBM Corporation */
22 (((uint32_t)(sizeof(struct siw_rreq_pkt) - \
27 struct siw_pbl *pbl = mem->pbl; in siw_get_pblpage()
28 u64 offset = addr - mem->va; in siw_get_pblpage()
40 if (!mem->is_pbl) in siw_get_page()
41 return siw_get_upage(mem->umem, sge->laddr + offset); in siw_get_page()
43 return siw_get_pblpage(mem, sge->laddr + offset, pbl_idx); in siw_get_page()
51 struct siw_wqe *wqe = &c_tx->wqe_active; in siw_try_1seg()
52 struct siw_sge *sge = &wqe->sqe.sge[0]; in siw_try_1seg()
[all …]
/linux/drivers/char/tpm/
H A Dtpm_tis_i2c_cr50.c1 // SPDX-License-Identifier: GPL-2.0
10 * - Use an interrupt for transaction status instead of hardcoded delays.
11 * - Must use write+wait+read read protocol.
12 * - All 4 bytes of status register must be read/written at once.
13 * - Burst count max is 63 bytes, and burst count behaves slightly differently
15 * - When reading from FIFO the full burstcnt must be read instead of just
48 * struct tpm_i2c_cr50_priv_data - Driver private data.
63 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler.
77 struct tpm_i2c_cr50_priv_data *priv = dev_get_drvdata(&chip->dev); in tpm_cr50_i2c_int_handler()
79 complete(&priv->tpm_ready); in tpm_cr50_i2c_int_handler()
[all …]

1234567