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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dmediatek-thermal.txt1 * Mediatek Thermal
3 This describes the device tree binding for the Mediatek thermal controller
4 which measures the on-SoC temperatures. This device does not have its own ADC,
11 - compatible:
12 - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
13 - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
14 - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
15 - "mediatek,mt7622-thermal" : For MT7622 SoC
16 - "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
17 - "mediatek,mt7986-thermal" : For MT7986 SoC
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H A Dmediatek,lvts-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek SoC Low Voltage Thermal Sensor (LVTS)
10 - Balsam CHIHI <bchihi@baylibre.com>
13 LVTS is a thermal management architecture composed of three subsystems,
14 a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU),
15 a Converter - Low Voltage Thermal Sensor converter (LVTS), and
21 - mediatek,mt7988-lvts-ap
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8188.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2023 MediaTek Inc.
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
14 #include <dt-bindings/power/mediatek,mt8188-power.h>
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H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
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H A Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
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H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
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H A Dmt7986a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mt7986-clk.h>
10 #include <dt-bindings/reset/mt7986-resets.h>
11 #include <dt-bindings/phy/phy.h>
14 compatible = "mediatek,mt7986a";
15 interrupt-parent = <&gic>;
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H A Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
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H A Dmt7622.dtsi2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
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H A Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
21 stdout-path = "serial0:115200n8";
25 compatible = "pwm-backlight";
27 power-supply = <&reg_vsys>;
28 enable-gpios = <&pio 176 0>;
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H A Dmt8395-kontron-3-5-sbc-i1200.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
16 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
17 #include <dt-bindings/spmi/spmi.h>
20 model = "Kontron 3.5\"-SBC-i1200";
21 compatible = "kontron,3-5-sbc-i1200", "mediatek,mt8395", "mediatek,mt8195";
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H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Eddie Huang <eddie.huang@mediatek.com>
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
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H A Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
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H A Dmt8183-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
8 /dts-v1/;
13 model = "MediaTek MT8183 evaluation board";
14 chassis-type = "embedded";
15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
27 stdout-path = "serial0:921600n8";
30 reserved-memory {
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H A Dmt8173-elm.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2016 MediaTek Inc.
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/regulator/dlg,da9211-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "pwm-backlight";
27 power-supply = <&bl_fixed_reg>;
28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
30 pinctrl-names = "default";
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dmt6577_auxadc.txt1 * Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc (mt65xx/mt81xx/mt27xx)
5 in some Mediatek SoCs which among other things measures the temperatures
7 used by thermal controller which reads the temperatures from the AUXADC
9 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
10 for the Thermal Controller which holds a phandle to the AUXADC.
13 - compatible: Should be one of:
14 - "mediatek,mt2701-auxadc": For MT2701 family of SoCs
15 - "mediatek,mt2712-auxadc": For MT2712 family of SoCs
16 - "mediatek,mt6765-auxadc": For MT6765 family of SoCs
17 - "mediatek,mt7622-auxadc": For MT7622 family of SoCs
[all …]
H A Dmediatek,mt2701-auxadc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/mediatek,mt2701-auxadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek AUXADC - ADC on Mediatek mobile SoC (mt65xx/mt81xx/mt27xx)
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Matthias Brugger <matthias.bgg@gmail.com>
15 in some Mediatek SoCs which among other things measures the temperatures
17 used by thermal controller which reads the temperatures from the AUXADC
18 directly via its own bus interface. See mediatek-thermal bindings
[all …]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
5 * Sean Wang <sean.wang@mediatek.com>
6 * Ryder Lee <ryder.lee@mediatek.com>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
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H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Erin.Lo <erin.lo@mediatek.com>
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
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/freebsd/sys/contrib/device-tree/Bindings/nvmem/
H A Dmtk-efuse.txt1 = Mediatek MTK-EFUSE device tree bindings =
3 This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
6 - compatible: should be
7 "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
8 "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
9 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
10 "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
11 "mediatek,mt8195-efuse", "mediatek,efuse": for MT8195
12 "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516
13 - reg: Should contain registers location and length
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmediatek,mt8195-scpsys.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek System Control Processor System
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
13 MediaTek System Control Processor System (SCPSYS) has several
15 domain control, thermal measurement, DVFS, etc.
20 - enum:
21 - mediatek,mt8167-scpsys
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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-mediatek.txt1 Binding for MediaTek's CPUFreq driver
5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
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/freebsd/sys/contrib/device-tree/Bindings/soc/mediatek/
H A Dscpsys.txt1 MediaTek SCPSYS
5 related tasks in the system. The tasks include thermal measurement, dynamic
11 power/power-domain.yaml. It provides the power domains defined in
12 - include/dt-bindings/power/mt8173-power.h
13 - include/dt-bindings/power/mt6797-power.h
14 - include/dt-bindings/power/mt6765-power.h
15 - include/dt-bindings/power/mt2701-power.h
16 - include/dt-bindings/power/mt2712-power.h
17 - include/dt-bindings/power/mt7622-power.h
20 - compatible: Should be one of:
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H A Dmtk-svs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mt
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dinit.c1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
6 #include <linux/hwmon-sysfs.h>
7 #include <linux/thermal.h>
18 switch (to_sensor_dev_attr(attr)->index) { in mt7921_thermal_temp_show()
21 struct mt792x_dev *mdev = phy->dev; in mt7921_thermal_temp_show()
34 return -EINVAL; in mt7921_thermal_temp_show()
47 struct wiphy *wiphy = phy->mt76->hw->wiphy; in mt7921_thermal_init()
54 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7921_%s", in mt7921_thermal_init()
57 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, in mt7921_thermal_init()
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