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/linux/drivers/net/dsa/realtek/
H A Drealtek-smi.c5 * The SMI protocol piggy-backs the MDIO MDC and MDIO signals levels
57 gpiod_direction_output(priv->mdc, 0); in realtek_smi_start()
62 gpiod_set_value(priv->mdc, 1); in realtek_smi_start()
64 gpiod_set_value(priv->mdc, 0); in realtek_smi_start()
68 gpiod_set_value(priv->mdc, 1); in realtek_smi_start()
72 gpiod_set_value(priv->mdc, 0); in realtek_smi_start()
81 gpiod_set_value(priv->mdc, 1); in realtek_smi_stop()
85 gpiod_set_value(priv->mdc, 1); in realtek_smi_stop()
87 gpiod_set_value(priv->mdc, 0); in realtek_smi_stop()
89 gpiod_set_value(priv->mdc, 1); in realtek_smi_stop()
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
10 - sys: MDC system interface clock.
28 mdc: dma-controller@18143000 {
29 compatible = "img,pistachio-mdc-dma";
54 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
/linux/include/linux/
H A Dsxgbe_platform.h15 /* MDC Clock Selection define*/
16 #define SXGBE_CSR_100_150M 0x0 /* MDC = clk_scr_i/62 */
17 #define SXGBE_CSR_150_250M 0x1 /* MDC = clk_scr_i/102 */
18 #define SXGBE_CSR_250_300M 0x2 /* MDC = clk_scr_i/122 */
19 #define SXGBE_CSR_300_350M 0x3 /* MDC = clk_scr_i/142 */
20 #define SXGBE_CSR_350_400M 0x4 /* MDC = clk_scr_i/162 */
21 #define SXGBE_CSR_400_500M 0x5 /* MDC = clk_scr_i/202 */
H A Dstmmac.h30 /* MDC Clock Selection define*/
31 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
32 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
33 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
34 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
35 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
36 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
50 /* The MDC clock could be set higher than the IEEE 802.3
54 * supporting higher MDC clocks.
55 * The MDC clock selection macros need to be defined for MDC clock rate
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt92 …i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc)
93 …0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc)
95 …, au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc)
119 …pi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act…
122 mpp31 31 gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc)
125 …, sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), ms…
127 …i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq)…
128 …(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq)…
132 …s_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act…
133 …tect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act…
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-cp110.c62 MPP_FUNCTION(10, "ge", "mdc")),
74 MPP_FUNCTION(10, "xg", "mdc")),
97 MPP_FUNCTION(10, "ge", "mdc")),
266 MPP_FUNCTION(8, "ge", "mdc"),
301 MPP_FUNCTION(8, "ge", "mdc")),
333 MPP_FUNCTION(7, "ge", "mdc"),
356 MPP_FUNCTION(7, "xg", "mdc"),
357 MPP_FUNCTION(8, "ge", "mdc"),
368 MPP_FUNCTION(7, "ge", "mdc"),
369 MPP_FUNCTION(8, "xg", "mdc"),
[all …]
/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi120 dmas = <&mdc 30 0xffffffff 0>;
136 dmas = <&mdc 23 0xffffffff 0>;
156 dmas = <&mdc 16 0xffffffff 0>;
173 dmas = <&mdc 14 0xffffffff 0>;
192 dmas = <&mdc 15 0xffffffff 0>;
217 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
232 dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
817 mdc: dma-controller@18143000 { label
818 compatible = "img,pistachio-mdc-dma";
882 dmas = <&mdc 8 0xffffffff 0>;
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-98dx3236-pinctrl.txt18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
45 mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
H A Dmarvell,armada-38x-pinctrl.txt22 mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
33 mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi)
74 mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
H A Dmarvell,armada-39x-pinctrl.txt22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
25 mpp7 7 gpio, dev(ad9), xsmi(mdc)
38 mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-img-spfi.txt34 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
/linux/Documentation/devicetree/bindings/net/
H A Dfsl,cpm-mdio.yaml30 fsl,mdc-pin:
53 fsl,mdc-pin = <13>;
H A Dfsl,fman-mdio.yaml33 from which the MDC frequency is derived.
50 become corrupt unless it is read within 16 MDC cycles
/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts149 0 2 1 0 1 0 /* MDC */
175 0 2 1 0 1 0 /* MDC */
201 0 2 1 0 1 0 /* MDC */
221 0 2 1 0 1 0 /* MDC */
239 0 2 1 0 1 0 /* MDC */
257 0 2 1 0 1 0 /* MDC */
275 0 2 1 0 1 0 /* MDC */
/linux/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-bitbang.c87 static inline void mdc(struct mdiobb_ctrl *ctrl, int what) in mdc() function
102 .set_mdc = mdc,
133 data = of_get_property(np, "fsl,mdc-pin", &len); in fs_mii_bitbang_init()
/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_mdio.c41 * axienet_mdio_mdc_enable - MDIO MDC enable function
44 * Enable the MDIO MDC. Called prior to a read/write operation
53 * axienet_mdio_mdc_disable - MDIO MDC disable function
56 * Disable the MDIO MDC. Called after a read/write operation
/linux/drivers/net/mdio/
H A Dmdio-ipq4019.c229 /* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1) in ipq4019_mdio_set_div()
277 /* Restore MDC rate */ in ipq_mdio_reset()
288 /* MDC rate defined in DT, we don't have to decide a default value */ in ipq4019_mdio_select_mdc_rate()
312 * try to find one MDC rate that is close the 802.3 spec of in ipq4019_mdio_select_mdc_rate()
/linux/drivers/s390/cio/
H A Ddevice_ops.c653 int mdc = 0, i; in ccw_device_get_mdc() local
676 mdc = 1; in ccw_device_get_mdc()
677 mdc = mdc ? min_t(int, mdc, chp->desc_fmt1.mdc) : in ccw_device_get_mdc()
678 chp->desc_fmt1.mdc; in ccw_device_get_mdc()
682 return mdc; in ccw_device_get_mdc()
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4018-jalapeno.dts21 mdc-pins {
23 function = "mdc";
H A Dqcom-ipq4018-ap120c-ac.dtsi45 mdc-pins {
47 function = "mdc";
/linux/drivers/net/ethernet/freescale/
H A Dxgmac_mdio.c231 * must read back the data register within 16 MDC cycles. in xgmac_mdio_read_c22()
297 * must read back the data register within 16 MDC cycles. in xgmac_mdio_read_c45()
339 dev_err(dev, "Input clock unknown, not changing MDC frequency"); in xgmac_mdio_set_mdc_freq()
345 dev_err(dev, "Requested MDC frequency is out of range, ignoring"); in xgmac_mdio_set_mdc_freq()
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-sq201.dts58 /* Uses MDC and MDIO */
59 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
H A Dgemini-sl93512r.dts73 /* Uses MDC and MDIO */
74 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
/linux/arch/arm/boot/dts/st/
H A Dstm32mp151a-prtt1l.dtsi40 /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce
41 * stmmac MDC clock without reducing system bus rate, we need to use
/linux/Documentation/devicetree/bindings/sound/
H A Dimg,spdif-in.txt36 dmas = <&mdc 15 0xffffffff 0>;

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