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/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dfsl,cpm-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,cpm-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,pq1-fec-mdio
17 - fsl,cpm2-mdio-bitbang
18 - items:
19 - const: fsl,mpc8272ads-mdio-bitbang
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/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
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H A Dmgcoge.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
28 d-cache-line-size = <32>;
29 i-cache-line-size = <32>;
30 d-cache-size = <16384>;
31 i-cache-size = <16384>;
[all …]
H A Dksi8560.dts15 /dts-v1/;
22 #address-cells = <1>;
23 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
38 d-cache-line-size = <32>;
39 i-cache-line-size = <32>;
40 d-cache-size = <0x8000>; /* L1, 32K */
41 i-cache-size = <0x8000>; /* L1, 32K */
42 timebase-frequency = <0>; /* From U-boot */
[all …]
H A Dmpc832x_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <16384>; // L1, 16K
34 i-cache-size = <16384>; // L1, 16K
[all …]
/linux/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/mdio-bitbang.h>
60 bb_set(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
62 bb_clr(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
65 in_be32(bitbang->dir); in mdio_dir()
71 return bb_read(bitbang->dat, bitbang->mdio_msk); in mdio_read()
79 bb_set(bitbang->dat, bitbang->mdio_msk); in mdio()
81 bb_clr(bitbang->dat, bitbang->mdio_msk); in mdio()
84 in_be32(bitbang->dat); in mdio()
87 static inline void mdc(struct mdiobb_ctrl *ctrl, int what) in mdc() function
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,ipq5018-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm IPQ5018 TLMM pin controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
18 const: qcom,ipq5018-tlmm
26 gpio-reserved-ranges:
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H A Dqcom,ipq8074-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm IPQ8074 TLMM pin controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.
18 const: qcom,ipq8074-pinctrl
26 gpio-reserved-ranges:
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H A Dqcom,ipq4019-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC.
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,ipq4019-pinctrl
28 gpio-reserved-ranges: true
31 "-state$":
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H A Dqcom,ipq9574-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC.
18 const: qcom,ipq9574-tlmm
26 gpio-reserved-ranges:
30 gpio-line-names:
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/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-cp110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "pinctrl-mvebu.h"
22 * Even if the pin controller is the same the MMP available depend on the SoC
24 * - In Armada7K (single CP) almost all the MPPs are available (except the
26 * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
27 * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
62 MPP_FUNCTION(10, "ge", "mdc")),
74 MPP_FUNCTION(10, "xg", "mdc")),
97 MPP_FUNCTION(10, "ge", "mdc")),
266 MPP_FUNCTION(8, "ge", "mdc"),
[all …]
H A Dpinctrl-armada-xp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * available: mv78230, mv78260 and mv78460. From a pin muxing
26 #include "pinctrl-mvebu.h"
189 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
235 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
243 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
371 MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
466 MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS),
467 MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
[all …]
H A Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
17 #address-cells = <1>;
18 #size-cells = <1>;
28 stdout-path = &uart0;
32 compatible = "gpio-keys";
34 button-wps {
[all …]
H A Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
/linux/arch/powerpc/platforms/pasemi/
H A Dgpio_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
9 * Based on drivers/net/fs_enet/mii-bitbang.c.
34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin)
35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin)
124 /* tri-state our MDIO I/O pin so we can read */ in gpio_mdio_read()
190 * Tri-state the MDIO line. in gpio_mdio_write()
202 /*nothing here - dunno how to reset it*/ in gpio_mdio_reset()
209 struct device *dev = &ofdev->dev; in gpio_mdio_probe()
210 struct device_node *np = ofdev->dev.of_node; in gpio_mdio_probe()
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
/linux/drivers/pinctrl/bcm/
H A Dpinctrl-ns.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/pinctrl/pinconf-generic.h>
44 { 6, "mdc", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
172 return -EINVAL; in ns_pinctrl_set_mux()
174 for (i = 0; i < group->grp.npins; i++) in ns_pinctrl_set_mux()
175 unset |= BIT(group->grp.pins[i]); in ns_pinctrl_set_mux()
177 tmp = readl(ns_pinctrl->base); in ns_pinctrl_set_mux()
179 writel(tmp, ns_pinctrl->base); in ns_pinctrl_set_mux()
196 .name = "pinctrl-ns",
202 { .compatible = "brcm,bcm4708-pinmux", .data = (void *)FLAG_BCM4708, },
[all …]
H A Dpinctrl-nsp-mux.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
10 * gpio_a (8 - 11)
11 * +----------
13 * gpio_a (8-11) | gpio_b (0 - 3)
14 * ------------------------+-------+----------
16 * | pwm (0 - 3)
17 * +----------
27 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
[all …]
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-ipq4019.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "pinctrl-msm.h"
115 #define DECLARE_QCA_GPIO_PINS(pin) \ argument
116 static const unsigned int gpio##pin##_pins[] = { pin }
502 QCA_PIN_FUNCTION(mdc),
532 PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
619 PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA,
703 { .compatible = "qcom,ipq4019-pinctrl", },
709 .name = "ipq4019-pinctrl",
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8568mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8568si-pre.dtsi"
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "cfi-flash";
38 bank-width = <2>;
39 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "fsl,mpc8568mds-bcsr";
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the EP93xx pin controller
4 * based on linux/drivers/pinctrl/pinmux-gemini.c
8 * This is a group-only pin controller.
23 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
30 #define DRIVER_NAME "pinctrl-ep93xx"
49 struct ep93xx_regmap_adev *aux = pmx->aux_dev; in ep93xx_pinctrl_update_bits()
51 aux->update_bits(aux->map, aux->lock, reg, mask, val); in ep93xx_pinctrl_update_bits()
71 * registers. These registers provide the selection of several pin multiplexing options and also
[all …]

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