| /linux/drivers/bus/fsl-mc/ |
| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Freescale Management Complex (MC) bus drivers
7 obj-$(CONFIG_FSL_MC_BUS) += mc-bus-driver.o
9 mc-bus-driver-objs := fsl-mc-bus.o \
10 mc-sys.o \
11 mc-io.o \
15 dprc-driver.o \
16 fsl-mc-allocator.o \
17 fsl-mc-msi.o \
19 obj-api.o
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| H A D | dprc-driver.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
6 * Copyright 2019-2020 NXP
14 #include <linux/fsl/mc.h>
16 #include "fsl-mc-private.h"
28 return mc_dev->obj_desc.id == obj_desc->id && in fsl_mc_device_match()
29 strcmp(mc_dev->obj_desc.type, obj_desc->type) == 0; in fsl_mc_device_match()
34 if (strcmp(obj->type, "dpmcp") == 0 || in fsl_mc_obj_desc_is_allocatable()
35 strcmp(obj->type, "dpcon") == 0 || in fsl_mc_obj_desc_is_allocatable()
36 strcmp(obj->type, "dpbp") == 0) in fsl_mc_obj_desc_is_allocatable()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # DPAA2 fsl-mc bus
5 # Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
9 bool "QorIQ DPAA2 fsl-mc bus driver"
13 Driver to enable the bus infrastructure for the QorIQ DPAA2
14 architecture. The fsl-mc bus driver handles discovery of
19 bool "Management Complex (MC) userspace support"
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| H A D | mc-io.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2013-2016 Freescale Semiconductor Inc.
8 #include <linux/fsl/mc.h>
10 #include "fsl-mc-private.h"
17 if (mc_io->dpmcp_dev) in fsl_mc_io_set_dpmcp()
18 return -EINVAL; in fsl_mc_io_set_dpmcp()
20 if (dpmcp_dev->mc_io) in fsl_mc_io_set_dpmcp()
21 return -EINVAL; in fsl_mc_io_set_dpmcp()
25 dpmcp_dev->obj_desc.id, in fsl_mc_io_set_dpmcp()
26 &dpmcp_dev->mc_handle); in fsl_mc_io_set_dpmcp()
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| H A D | fsl-mc-allocator.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * fsl-mc object allocator driver
5 * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
11 #include <linux/fsl/mc.h>
13 #include "fsl-mc-private.h"
23 * fsl_mc_resource_pool_add_device - add allocatable object to a resource
24 * pool of a given fsl-mc bus
26 * @mc_bus: pointer to the fsl-mc bus
28 * @mc_dev: pointer to allocatable fsl-mc device
39 struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; in fsl_mc_resource_pool_add_device()
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| H A D | fsl-mc-private.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Freescale Management Complex (MC) bus private declarations
11 #include <linux/fsl/mc.h>
190 /* response word 3-4 */
192 /* response word 5-6 */
202 /* cmd word 1-2 */
204 /* cmd word 3-4 */
221 /* base_addr may be zero if older MC firmware is used */
235 /* cmd word 3-4 */
269 /* IRQ event - Indicates that a new object added to the container */
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| /linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| H A D | overview.rst | 16 DPAA2 is a hardware architecture designed for high-speeed network
22 A DPAA2 hardware component called the Management Complex (or MC) manages the
23 DPAA2 hardware resources. The MC provides an object-based abstraction for
25 The MC uses DPAA2 hardware resources such as queues, buffer pools, and
28 The MC provides memory-mapped I/O command interfaces (MC portals)
34 +--------------------------------------+
38 +-----------------------------|--------+
44 +------------------------| mc portal |-+
46 | +- - - - - - - - - - - - -V- - -+ |
48 | | Management Complex (MC) | |
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| H A D | dpio-driver.rst | 7 :Copyright: |copy| 2016-2018 NXP
29 ---------------
31 The DPIO driver is bound to DPIO objects discovered on the fsl-mc bus and
40 The Linux DPIO driver consists of 3 primary components--
41 DPIO object driver-- fsl-mc driver that manages the DPIO object
43 DPIO service-- provides APIs to other Linux drivers for services
45 QBman portal interface-- sends portal commands, gets responses::
47 fsl-mc other
48 bus drivers
50 +---+----+ +------+-----+
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| H A D | mac-phy-support.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 --------
14 drivers (dpaa2-eth, dpaa2-ethsw) interact with the PHY library.
17 ---------------------------
19 Among other DPAA2 objects, the fsl-mc bus exports DPNI objects (abstracting a
20 network interface) and DPMAC objects (abstracting a MAC). The dpaa2-eth driver
26 directly by the dpaa2-eth driver or by phylink.
28 .. code-block:: none
30 Sources of abstracted link state information presented by the MC firmware
32 +--------------------------------------+
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-fsl-mc | 1 What: /sys/bus/fsl-mc/drivers/.../bind
8 and is the same as found in /sys/bus/fsl-mc/devices/.
12 # echo dpni.2 > /sys/bus/fsl-mc/drivers/fsl_dpaa2_eth/bind
14 What: /sys/bus/fsl-mc/drivers/.../unbind
21 and is the same as found in /sys/bus/fsl-mc/devices/.
25 # echo dpni.2 > /sys/bus/fsl-mc/drivers/fsl_dpaa2_eth/unbind
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| /linux/Documentation/ABI/stable/ |
| H A D | sysfs-bus-fsl-mc | 1 What: /sys/bus/fsl-mc/rescan
5 Description: Writing a non-zero value to this attribute will
6 force a rescan of fsl-mc bus in the system and
7 synchronize the objects under fsl-mc bus and the
11 What: /sys/bus/fsl-mc/autorescan
17 of the fsl-mc bus is performed. A non-zero value
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| /linux/Documentation/driver-api/ |
| H A D | ipmb.rst | 2 IPMB Driver for a Satellite MC
5 The Intelligent Platform Management Bus or IPMB, is an
6 I2C bus that provides a standardized interconnection between
10 IPMB bus.
15 hot-swapping disk drivers in the system chassis, etc...
20 Controller or Satellite MC) via IPMB and the device
26 IPMB driver for Satellite MC
27 ----------------------------
29 ipmb-dev-int - This is the driver needed on a Satellite MC to
35 function to set the Satellite MC as an I2C slave.
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| /linux/drivers/slimbus/ |
| H A D | slimbus.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2011-2017, The Linux Foundation
26 * BYTE 1: RSVD[7] MC[6:0]
79 /* Indicate that the frequency of the flow and the bus frequency are locked */
91 * struct slim_framer - Represents SLIMbus framer.
93 * responsible for clocking the bus.
94 * Manager is responsible for framer hand-over.
98 * frequency ('clock gear 10') at which the bus can operate.
111 * struct slim_msg_txn - Message to be sent by the controller.
116 * @mc: Header field. LSB is message code for type mt.
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| /linux/include/linux/fsl/ |
| H A D | mc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Freescale Management Complex (MC) bus public interface
5 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
6 * Copyright 2019-2020 NXP
27 * struct fsl_mc_driver - MC object device driver object
44 * with a DPRC bus. This structure is to be embedded in each device-specific
62 * enum fsl_mc_pool_type - Types of allocatable MC bus resources
68 FSL_MC_POOL_DPMCP = 0x0, /* corresponds to "dpmcp" in the MC */
69 FSL_MC_POOL_DPBP, /* corresponds to "dpbp" in the MC */
70 FSL_MC_POOL_DPCON, /* corresponds to "dpcon" in the MC */
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| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | fsl,qoriq-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | fsl,qoriq-mc-dpmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 pcs-handle:
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| /linux/arch/mips/sgi-ip22/ |
| H A D | ip22-berr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ip22-berr.c: Bus error handling.
5 * Copyright (C) 2002, 2003 Ladislav Michl (ladis@linux-mips.org)
16 #include <asm/sgi/mc.h>
27 static unsigned int hpc3_berr_stat; /* Bus error interrupt status */
32 cpu_err_addr = sgimc->cerr; in save_and_clear_buserr()
33 cpu_err_stat = sgimc->cstat; in save_and_clear_buserr()
34 gio_err_addr = sgimc->gerr; in save_and_clear_buserr()
35 gio_err_stat = sgimc->gstat; in save_and_clear_buserr()
36 extio_stat = ip22_is_fullhouse() ? sgioc->extio : (sgint->errstat << 4); in save_and_clear_buserr()
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| H A D | ip28-berr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ip28-berr.c: Bus error handling.
5 * Copyright (C) 2002, 2003 Ladislav Michl (ladis@linux-mips.org)
6 * Copyright (C) 2005 Peter Fuerst (pf@net.alphadv.de) - IP28
21 #include <asm/sgi/mc.h>
39 static unsigned int hpc3_berr_stat; /* Bus error interrupt status */
69 * Starting with a bus-address, save secondary cache (indexed by in save_cache_tags()
84 * might fit to this bus-address, knowing that VA[11:0] == PA[11:0]. in save_cache_tags()
89 addr &= (0xffL << 56) | ((1 << 12) - 1); in save_cache_tags()
105 addr &= (0xffL << 56) | ((1 << 12) - 1); in save_cache_tags()
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| /linux/arch/mips/include/asm/sgi/ |
| H A D | mc.h | 6 * mc.h: Definitions for SGI Memory Controller
23 #define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
28 #define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */
29 #define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */
33 #define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
40 #define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
52 volatile u32 systemid; /* MC system ID register, readonly */
53 #define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */
54 #define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */
64 #define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
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| /linux/drivers/edac/ |
| H A D | i10nm_base.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <asm/intel-family.h>
24 pci_read_config_dword((d)->uracu, 0xd0, &(reg))
26 pci_read_config_dword((d)->uracu, \
27 (res_cfg->type == GNR ? 0xd4 : 0xd8) + (i) * 4, &(reg))
29 pci_read_config_dword((d)->sad_all, (offset) + (i) * \
30 (res_cfg->type == GNR ? 12 : 8), &(reg))
32 pci_read_config_dword((d)->uracu, 0xd4, &(reg))
34 pci_read_config_dword((d)->pcu_cr3, \
35 res_cfg->type == GNR ? 0x290 : 0x90, &(reg))
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| H A D | skx_common.c | 1 // SPDX-License-Identifier: GPL-2.0
10 * when linked once into a module and into a built-in object, at the
12 * file is being linked into a built-in object.
63 return -ENODEV; in skx_adxl_get()
84 skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n"); in skx_adxl_get()
97 return -ENOMEM; in skx_adxl_get()
104 return -ENOMEM; in skx_adxl_get()
115 return -ENODEV; in skx_adxl_get()
135 for (int i = 0; i < d->num_imc; i++) in skx_init_mc_mapping()
136 d->imc[i].mc_mapping = i; in skx_init_mc_mapping()
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
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| /linux/Documentation/devicetree/bindings/firmware/ |
| H A D | nvidia,tegra186-bpmp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
33 - <dt-bindings/clock/tegra186-clock.h>
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| /linux/drivers/bus/ |
| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the bus drivers.
6 # Interconnect bus drivers for ARM platforms
7 obj-$(CONFIG_ARM_CCI) += arm-cci.o
8 obj-$(CONFIG_ARM_INTEGRATOR_LM) += arm-integrator-lm.o
9 obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o
10 obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
11 obj-$(CONFIG_MOXTET) += moxtet.o
13 # DPAA2 fsl-mc bus
14 obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/
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| /linux/Documentation/userspace-api/media/ |
| H A D | glossary.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
30 Unit of data transported by a bus. On parallel buses, the data unit
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
72 together make a larger user-facing functional peripheral. For
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
83 serial computer bus used to control some hardware components
84 like sub-device hardware components.
86 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
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