| /freebsd/sys/dev/dpaa2/ |
| H A D | dpaa2_mc_fdt.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2022 Dmitry Salychev
31 * The DPAA2 Management Complex (MC) Bus Driver (FDT-based).
33 * MC is a hardware resource manager which can be found in several NXP
35 * hardware objects used in network-oriented packet processing applications.
40 #include <sys/bus.h>
46 #include <machine/bus.h>
73 compatible = "fsl,qoriq-mc-dpmac";
76 pcs-handle = <0x15>;
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| H A D | dpaa2_mc.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2022 Dmitry Salychev
32 #include <sys/bus.h>
51 * Maximum number of MSIs supported by the MC for its children without IOMMU.
58 #define DPAA2_MC_DEV_ALLOCATABLE 0x01u /* to be managed by DPAA2-specific rman */
65 * @brief Software context for the DPAA2 Management Complex (MC) driver.
72 * res: Unmapped MC command portal and control registers resources.
73 * map: Mapped MC command portal and control registers resources.
78 * dpmcp_rman: MC portals resource manager.
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| H A D | dpaa2_mc.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2022 Dmitry Salychev
30 * The DPAA2 Management Complex (MC) bus driver.
32 * MC is a hardware resource manager which can be found in several NXP
34 * hardware objects used in network-oriented packet processing applications.
42 #include <sys/bus.h>
52 #include <machine/bus.h>
72 /* Macros to read/write MC registers */
73 #define mcreg_read_4(_sc, _r) bus_read_4(&(_sc)->map[1], (_r))
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| H A D | dpaa2_mcp.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2022 Dmitry Salychev
30 * DPAA2 MC command portal and helper routines.
35 #include <sys/bus.h>
45 #include <machine/bus.h>
77 mtx_init(&p->lock, "mcp_sleep_lock", NULL, MTX_DEF); in dpaa2_mcp_init_portal()
79 p->res = res; in dpaa2_mcp_init_portal()
80 p->map = map; in dpaa2_mcp_init_portal()
81 p->flags = flags; in dpaa2_mcp_init_portal()
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| H A D | dpaa2_con.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2022 Dmitry Salychev
47 #include <sys/bus.h>
55 #include <machine/bus.h>
73 * NOTE: MC command portals (MCPs) are used to send commands to, and
74 * receive responses from, the MC firmware. One portal per DPCON.
79 /* --- */
81 /* --- */
120 sc->dev = dev; in dpaa2_con_attach()
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| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | fsl,qoriq-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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| H A D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
43 - compatible
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | fsl,qoriq-mc-dpmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 pcs-handle:
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
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| H A D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
16 handles memory requests for 40-bit virtual addresses from internal clients
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | fsl-ls208xa.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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| H A D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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| H A D | fsl-ls1088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | nvidia,tegra186-bpmp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpm
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| /freebsd/sys/contrib/device-tree/src/arm64/nvidia/ |
| H A D | tegra194.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gi
662 mc: memory-controller@2c00000 { global() label
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| /freebsd/sys/contrib/device-tree/Bindings/perf/ |
| H A D | apm-xgene-pmu.txt | 1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
6 L3C - L3 cache controller
7 IOB - IO bridge
8 MCB - Memory controller bridge
9 MC - Memory controller
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
16 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
17 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
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| /freebsd/sys/contrib/device-tree/Bindings/display/tegra/ |
| H A D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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| /freebsd/sys/contrib/device-tree/Bindings/interconnect/ |
| H A D | qcom,rpmh.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
11 - Odelu Kukatla <quic_okukatla@quicinc.com>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
27 - qcom,sc7180-aggre1-noc
28 - qcom,sc7180-aggre2-noc
29 - qcom,sc7180-camnoc-virt
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| /freebsd/sys/dev/mlx/ |
| H A D | mlx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include <sys/bus.h>
47 #include <machine/bus.h>
66 * Per-interface accessor methods
68 static int mlx_v3_tryqueue(struct mlx_softc *sc, struct mlx_command *mc);
73 static int mlx_v4_tryqueue(struct mlx_softc *sc, struct mlx_command *mc);
78 static int mlx_v5_tryqueue(struct mlx_softc *sc, struct mlx_command *mc);
87 static void mlx_periodic_enquiry(struct mlx_command *mc);
89 static void mlx_periodic_eventlog_respond(struct mlx_command *mc);
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| /freebsd/sys/contrib/device-tree/Bindings/gpu/host1x/ |
| H A D | nvidia,tegra210-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 and newer chips. It is located on the Host1x bus and typically
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
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| H A D | nvidia,tegra210-nvjpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 and newer chips. It is located on the Host1x bus and typically programmed
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvjpg@[0-9a-f]*$"
24 - nvidia,tegra210-nvjpg
25 - nvidia,tegra186-nvjpg
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| H A D | nvidia,tegra210-nvenc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 and newer chips. It is located on the Host1x bus and typically
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
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| H A D | nvidia,tegra234-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 and newer chips. It is located on the Host1x bus and typically
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
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| /freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
| H A D | tegra30.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc
918 mc: memory-controller@7000f000 { global() label
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| /freebsd/sys/contrib/device-tree/Bindings/edac/ |
| H A D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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