| /linux/drivers/gpu/drm/nouveau/nvkm/falcon/ |
| H A D | gm200.c | 221 u32 mbox0, mbox1; in gm200_flcn_fw_boot() local
237 mbox0 = nvkm_falcon_rd32(falcon, 0x040); in gm200_flcn_fw_boot()
239 if (FLCN_ERRON(falcon, ret || mbox0 != mbox0_ok, "mbox %08x %08x", mbox0, mbox1)) in gm200_flcn_fw_boot()
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| H A D | ga102.c | 113 ga102_flcn_fw_boot(struct nvkm_falcon_fw *fw, u32 *mbox0, u32 *mbox1, u32 mbox0_ok, u32 irqsclr) in ga102_flcn_fw_boot() argument
122 return gm200_flcn_fw_boot(fw, mbox0, mbox1, mbox0_ok, irqsclr); in ga102_flcn_fw_boot()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ |
| H A D | fwsec.c | 273 u32 mbox0 = 0; in nvkm_gsp_fwsec() local
307 ret = nvkm_falcon_fw_boot(&fw, subdev, true, &mbox0, NULL, 0, 0); in nvkm_gsp_fwsec()
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| /linux/drivers/scsi/ |
| H A D | qlogicpti.c | 212 case 1: sbus_writew(param[0], qpti->qregs + MBOX0); in qlogicpti_mbox_command()
244 if (sbus_readw(qpti->qregs + MBOX0) & 0x4000) in qlogicpti_mbox_command()
253 while (--loop_count && (sbus_readw(qpti->qregs + MBOX0) == 0x04)) in qlogicpti_mbox_command()
271 case 1: param[0] = sbus_readw(qpti->qregs + MBOX0); in qlogicpti_mbox_command()
352 while (--loop_count && ((sbus_readw(qpti->qregs + MBOX0) & 0xff) == 0x04)) in qlogicpti_reset_hardware()
1144 switch (sbus_readw(qpti->qregs + MBOX0)) { in qlogicpti_intr_handler()
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| H A D | qlogicpti.h | 17 #define MBOX0 0x080UL macro
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| H A D | ncr53c8xx.h | 487 #define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
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| /linux/Documentation/driver-api/rapidio/ |
| H A D | tsi721.rst | 60 correspond to MBOX0 - MBOX3. MBOX is under driver's control if the
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| /linux/drivers/comedi/drivers/ |
| H A D | plx9080.h | 330 /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
590 * the MBOX0 and MBOX1 registers if the I2O feature is enabled, but MBOX0 and
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| /linux/drivers/gpu/drm/nouveau/include/nvkm/core/ |
| H A D | falcon.h | 101 u32 *mbox0, u32 *mbox1, u32 mbox0_ok, u32 irqsclr);
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| /linux/drivers/crypto/marvell/octeontx/ |
| H A D | otx_cptpf_main.c | 131 otx_cpt_mbx0_intr_handler, 0, "CPT Mbox0", cpt); in otx_cpt_register_interrupts()
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| /linux/drivers/net/ethernet/marvell/octeontx2/nic/ |
| H A D | cn20k.c | 244 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); in cn20k_register_pfvf_mbox_intr()
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| H A D | otx2_pf.c | 734 /* Register MBOX0 interrupt handler */ in otx2_register_pfvf_mbox_intr()
738 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pdev, pf->pcifunc)); in otx2_register_pfvf_mbox_intr()
740 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); in otx2_register_pfvf_mbox_intr()
745 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); in otx2_register_pfvf_mbox_intr()
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| /linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-sriox-defs.h | 455 uint64_t mbox0:2; member
461 uint64_t mbox0:2;
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| /linux/Documentation/scsi/ |
| H A D | ChangeLog.sym53c8xx | 459 - Define some new IO registers for the 896 (istat1, mbox0, mbox1)
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| /linux/drivers/scsi/sym53c8xx_2/ |
| H A D | sym_defs.h | 75 #define FE_ISTAT1 (1<<30) /* Have ISTAT1, MBOX0, MBOX1 registers */
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| /linux/drivers/clk/thead/ |
| H A D | clk-th1520-ap.c | 925 static CCU_GATE(CLK_MBOX0, mbox0_clk, "mbox0", apb3_cpusys_pclk_pd, 0x208, 7, 0);
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| /linux/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4_debugfs.c | 3784 { "mbox0", &mbox_debugfs_fops, 0600, 0 }, in t4_setup_debugfs()
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