| /linux/drivers/net/ethernet/cavium/liquidio/ |
| H A D | octeon_mailbox.c | 31 * @mbox: Pointer mailbox
33 * Reads the 8-bytes of data from the mbox register
36 int octeon_mbox_read(struct octeon_mbox *mbox) in octeon_mbox_read() argument
41 spin_lock(&mbox->lock); in octeon_mbox_read()
43 msg.u64 = readq(mbox->mbox_read_reg); in octeon_mbox_read()
46 spin_unlock(&mbox->lock); in octeon_mbox_read()
50 if (mbox->state & OCTEON_MBOX_STATE_REQUEST_RECEIVING) { in octeon_mbox_read()
51 mbox->mbox_req.data[mbox->mbox_req.recv_len - 1] = msg.u64; in octeon_mbox_read()
52 mbox->mbox_req.recv_len++; in octeon_mbox_read()
54 if (mbox->state & OCTEON_MBOX_STATE_RESPONSE_RECEIVING) { in octeon_mbox_read()
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| /linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | mbox.c | 13 #include "mbox.h"
18 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid) in __otx2_mbox_reset() argument
20 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in __otx2_mbox_reset()
24 tx_hdr = hw_mbase + mbox->tx_start; in __otx2_mbox_reset()
25 rx_hdr = hw_mbase + mbox->rx_start; in __otx2_mbox_reset()
36 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid) in otx2_mbox_reset() argument
38 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in otx2_mbox_reset()
41 __otx2_mbox_reset(mbox, devid); in otx2_mbox_reset()
46 void otx2_mbox_destroy(struct otx2_mbox *mbox) in otx2_mbox_destroy() argument
48 mbox->reg_base = NULL; in otx2_mbox_destroy()
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| /linux/drivers/soc/apple/ |
| H A D | mailbox.c | 99 int apple_mbox_send(struct apple_mbox *mbox, const struct apple_mbox_msg msg, in apple_mbox_send() argument
107 spin_lock_irqsave(&mbox->tx_lock, flags); in apple_mbox_send()
108 mbox_ctrl = readl_relaxed(mbox->regs + mbox->hw->a2i_control); in apple_mbox_send()
110 while (mbox_ctrl & mbox->hw->control_full) { in apple_mbox_send()
113 mbox->regs + mbox->hw->a2i_control, mbox_ctrl, in apple_mbox_send()
114 !(mbox_ctrl & mbox->hw->control_full), 100, in apple_mbox_send()
118 spin_unlock_irqrestore(&mbox->tx_lock, flags); in apple_mbox_send()
133 if (mbox->hw->has_irq_controls) { in apple_mbox_send()
134 writel_relaxed(mbox->hw->irq_bit_send_empty, in apple_mbox_send()
135 mbox->regs + mbox->hw->irq_ack); in apple_mbox_send()
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| /linux/drivers/mailbox/ |
| H A D | mailbox-altera.c | 60 static inline int altera_mbox_full(struct altera_mbox *mbox) in altera_mbox_full() argument
64 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_full()
68 static inline int altera_mbox_pending(struct altera_mbox *mbox) in altera_mbox_pending() argument
72 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_pending()
76 static void altera_mbox_rx_intmask(struct altera_mbox *mbox, bool enable) in altera_mbox_rx_intmask() argument
80 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
85 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
88 static void altera_mbox_tx_intmask(struct altera_mbox *mbox, bool enable) in altera_mbox_tx_intmask() argument
92 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
97 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
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| H A D | hi6220-mailbox.c | 90 static void mbox_set_state(struct hi6220_mbox *mbox, in mbox_set_state() argument
95 status = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
97 writel(status, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
100 static void mbox_set_mode(struct hi6220_mbox *mbox, in mbox_set_mode() argument
105 mode = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_mode()
107 writel(mode, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_mode()
113 struct hi6220_mbox *mbox = mchan->parent; in hi6220_mbox_last_tx_done() local
117 BUG_ON(mbox->tx_irq_mode); in hi6220_mbox_last_tx_done()
119 state = readl(mbox->base + MBOX_MODE_REG(mchan->slot)); in hi6220_mbox_last_tx_done()
126 struct hi6220_mbox *mbox = mchan->parent; in hi6220_mbox_send_data() local
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| H A D | omap-mailbox.c | 107 static u32 mbox_fifo_read(struct omap_mbox *mbox) in mbox_fifo_read() argument
109 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
111 return mbox_read_reg(mbox->parent, fifo->msg); in mbox_fifo_read()
114 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) in mbox_fifo_write() argument
116 struct omap_mbox_fifo *fifo = &mbox->tx_fifo; in mbox_fifo_write()
118 mbox_write_reg(mbox->parent, msg, fifo->msg); in mbox_fifo_write()
121 static int mbox_fifo_empty(struct omap_mbox *mbox) in mbox_fifo_empty() argument
123 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_empty()
125 return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); in mbox_fifo_empty()
128 static int mbox_fifo_full(struct omap_mbox *mbox) in mbox_fifo_full() argument
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| H A D | sun6i-msgbox.c | 44 #define mbox_dbg(mbox, ...) dev_dbg((mbox)->controller.dev, __VA_ARGS__) argument
58 return chan - chan->mbox->chans; in channel_number()
68 struct sun6i_msgbox *mbox = dev_id; in sun6i_msgbox_irq() local
73 status = readl(mbox->regs + LOCAL_IRQ_EN_REG) & in sun6i_msgbox_irq()
74 readl(mbox->regs + LOCAL_IRQ_STAT_REG); in sun6i_msgbox_irq()
80 struct mbox_chan *chan = &mbox->controller.chans[n]; in sun6i_msgbox_irq()
86 uint32_t msg = readl(mbox->regs + MSG_DATA_REG(n)); in sun6i_msgbox_irq()
88 mbox_dbg(mbox, "Channel %d received 0x%08x\n", n, msg); in sun6i_msgbox_irq()
93 writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG); in sun6i_msgbox_irq()
101 struct sun6i_msgbox *mbox = to_sun6i_msgbox(chan); in sun6i_msgbox_send_data() local
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| H A D | armada-37xx-rwtm-mailbox.c | 45 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_receive() local
49 rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); in a37xx_mbox_receive()
51 rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); in a37xx_mbox_receive()
59 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_irq_handler() local
62 reg = readl(mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
68 dev_err(mbox->dev, "Secure processor command queue full\n"); in a37xx_mbox_irq_handler()
70 writel(reg, mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
79 struct a37xx_mbox *mbox = chan->con_priv; in a37xx_mbox_send_data() local
87 reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); in a37xx_mbox_send_data()
89 dev_warn(mbox->dev, "Secure processor not ready\n"); in a37xx_mbox_send_data()
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| H A D | bcm2835-mailbox.c | 63 return container_of(link->mbox, struct bcm2835_mbox, controller); in bcm2835_link_mbox()
68 struct bcm2835_mbox *mbox = dev_id; in bcm2835_mbox_irq() local
69 struct device *dev = mbox->controller.dev; in bcm2835_mbox_irq()
70 struct mbox_chan *link = &mbox->controller.chans[0]; in bcm2835_mbox_irq()
72 while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) { in bcm2835_mbox_irq()
73 u32 msg = readl(mbox->regs + MAIL0_RD); in bcm2835_mbox_irq()
82 struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); in bcm2835_send_data() local
85 spin_lock(&mbox->lock); in bcm2835_send_data()
86 writel(msg, mbox->regs + MAIL1_WRT); in bcm2835_send_data()
87 dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); in bcm2835_send_data()
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| H A D | hi3660-mailbox.c | 25 #define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40)) argument
80 static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox) in to_hi3660_mbox() argument
82 return container_of(mbox, struct hi3660_mbox, controller); in to_hi3660_mbox()
88 struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); in hi3660_mbox_check_state() local
89 struct hi3660_chan_info *mchan = &mbox->mchan[ch]; in hi3660_mbox_check_state()
90 void __iomem *base = MBOX_BASE(mbox, ch); in hi3660_mbox_check_state()
102 dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__); in hi3660_mbox_check_state()
114 struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); in hi3660_mbox_unlock() local
118 writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG); in hi3660_mbox_unlock()
120 val = readl(mbox->base + MBOX_IPC_LOCK_REG); in hi3660_mbox_unlock()
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| H A D | mailbox.c | 77 /* Try to submit a message to the MBOX controller */ in msg_submit()
78 err = chan->mbox->ops->send_data(chan, data); in msg_submit()
88 spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags); in msg_submit()
89 hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL); in msg_submit()
90 spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags); in msg_submit()
120 struct mbox_controller *mbox = in txdone_hrtimer() local
126 for (i = 0; i < mbox->num_chans; i++) { in txdone_hrtimer()
127 struct mbox_chan *chan = &mbox->chans[i]; in txdone_hrtimer()
130 txdone = chan->mbox->ops->last_tx_done(chan); in txdone_hrtimer()
139 spin_lock_irqsave(&mbox->poll_hrt_lock, flags); in txdone_hrtimer()
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| H A D | mtk-adsp-mailbox.c | 19 struct mbox_controller mbox; member
31 static inline struct mtk_adsp_mbox_priv *get_mtk_adsp_mbox_priv(struct mbox_controller *mbox) in get_mtk_adsp_mbox_priv() argument
33 return container_of(mbox, struct mtk_adsp_mbox_priv, mbox); in get_mtk_adsp_mbox_priv()
39 struct mtk_adsp_mbox_priv *priv = get_mtk_adsp_mbox_priv(chan->mbox); in mtk_adsp_mbox_irq()
56 static struct mbox_chan *mtk_adsp_mbox_xlate(struct mbox_controller *mbox, in mtk_adsp_mbox_xlate() argument
59 return mbox->chans; in mtk_adsp_mbox_xlate()
64 struct mtk_adsp_mbox_priv *priv = get_mtk_adsp_mbox_priv(chan->mbox); in mtk_adsp_mbox_startup()
66 /* Clear ADSP mbox command */ in mtk_adsp_mbox_startup()
75 struct mtk_adsp_mbox_priv *priv = get_mtk_adsp_mbox_priv(chan->mbox); in mtk_adsp_mbox_shutdown()
77 /* Clear ADSP mbox command */ in mtk_adsp_mbox_shutdown()
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| H A D | arm_mhu_db.c | 41 struct mbox_controller mbox; member
59 mhu_db_mbox_to_channel(struct mbox_controller *mbox, unsigned int pchan, in mhu_db_mbox_to_channel() argument
65 for (i = 0; i < mbox->num_chans; i++) { in mhu_db_mbox_to_channel()
66 chan_info = mbox->chans[i].con_priv; in mhu_db_mbox_to_channel()
69 return &mbox->chans[i]; in mhu_db_mbox_to_channel()
99 struct mbox_controller *mbox = &mhu->mbox; in mhu_db_mbox_irq_to_channel() local
112 chan = mhu_db_mbox_to_channel(mbox, pchan, doorbell); in mhu_db_mbox_irq_to_channel()
115 dev_err(mbox->dev, in mhu_db_mbox_irq_to_channel()
168 struct mbox_controller *mbox = &chan_info->mhu->mbox; in mhu_db_shutdown() local
171 for (i = 0; i < mbox->num_chans; i++) in mhu_db_shutdown()
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| H A D | mailbox-sti.c | 42 * @mbox: Representation of a communication channel controller
55 struct mbox_controller *mbox; member
97 struct mbox_chan *sti_mbox_to_channel(struct mbox_controller *mbox, in sti_mbox_to_channel() argument
104 for (i = 0; i < mbox->num_chans; i++) { in sti_mbox_to_channel()
105 chan_info = mbox->chans[i].con_priv; in sti_mbox_to_channel()
109 return &mbox->chans[i]; in sti_mbox_to_channel()
112 dev_err(mbox->dev, in sti_mbox_to_channel()
163 struct mbox_controller *mbox = mdev->mbox; in sti_mbox_irq_to_channel() local
179 chan = sti_mbox_to_channel(mbox, instance, channel); in sti_mbox_irq_to_channel()
181 dev_dbg(mbox->dev, in sti_mbox_irq_to_channel()
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| /linux/drivers/net/ethernet/marvell/octeon_ep/ |
| H A D | octep_ctrl_mbox.c | 27 /* Size of mbox info in bytes */
29 /* Size of mbox host to fw queue info in bytes */
31 /* Size of mbox fw to host queue info in bytes */
74 int octep_ctrl_mbox_init(struct octep_ctrl_mbox *mbox) in octep_ctrl_mbox_init() argument
78 if (!mbox) in octep_ctrl_mbox_init()
81 if (!mbox->barmem) { in octep_ctrl_mbox_init()
82 pr_info("octep_ctrl_mbox : Invalid barmem %p\n", mbox->barmem); in octep_ctrl_mbox_init()
86 magic_num = readq(OCTEP_CTRL_MBOX_INFO_MAGIC_NUM(mbox->barmem)); in octep_ctrl_mbox_init()
92 status = readq(OCTEP_CTRL_MBOX_INFO_FW_STATUS(mbox->barmem)); in octep_ctrl_mbox_init()
98 fw_versions = readq(OCTEP_CTRL_MBOX_INFO_FW_VERSION(mbox->barmem)); in octep_ctrl_mbox_init()
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| /linux/drivers/crypto/marvell/octeontx2/ |
| H A D | otx2_cpt_mbox_common.c | 7 int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_mbox_msg() argument
11 otx2_mbox_msg_send(mbox, 0); in otx2_cpt_send_mbox_msg()
12 ret = otx2_mbox_wait_for_rsp(mbox, 0); in otx2_cpt_send_mbox_msg()
14 dev_err(&pdev->dev, "RVU MBOX timeout.\n"); in otx2_cpt_send_mbox_msg()
17 dev_err(&pdev->dev, "RVU MBOX error: %d.\n", ret); in otx2_cpt_send_mbox_msg()
24 int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_ready_msg() argument
28 req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), in otx2_cpt_send_ready_msg()
31 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n"); in otx2_cpt_send_ready_msg()
38 return otx2_cpt_send_mbox_msg(mbox, pdev); in otx2_cpt_send_ready_msg()
42 int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev) in otx2_cpt_send_af_reg_requests() argument
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| H A D | otx2_cptvf_mbox.c | 17 * Overwrite mbox mbase to point to bounce buffer, so that PF/VF in otx2_cpt_mbox_bbuf_init()
18 * prepare all mbox messages in bounce buffer instead of directly in otx2_cpt_mbox_bbuf_init()
19 * in hw mbox memory. in otx2_cpt_mbox_bbuf_init()
28 static void otx2_cpt_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) in otx2_cpt_sync_mbox_bbuf() argument
31 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); in otx2_cpt_sync_mbox_bbuf()
32 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; in otx2_cpt_sync_mbox_bbuf()
39 hdr = hw_mbase + mbox->rx_start; in otx2_cpt_sync_mbox_bbuf()
42 if (msg_size > mbox->rx_size - msgs_offset) in otx2_cpt_sync_mbox_bbuf()
43 msg_size = mbox->rx_size - msgs_offset; in otx2_cpt_sync_mbox_bbuf()
45 /* Copy mbox messages from mbox memory to bounce buffer */ in otx2_cpt_sync_mbox_bbuf()
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| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | ti,omap-mailbox.yaml | 56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
60 The equivalent "mbox-names" property value can be used to give a name to the
64 omap-mbox-descriptor:
67 The omap-mbox-descriptor is made of up of 3 cells and represents a single
72 mailbox fifo id used either for transmitting on ti,mbox-tx channel or
73 for receiving on ti,mbox-rx channel (fifo_id). This is the hardware
96 ti,mbox-tx:
97 $ref: "#/$defs/omap-mbox-descriptor"
100 ti,mbox-rx:
101 $ref: "#/$defs/omap-mbox-descriptor"
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| /linux/drivers/net/ethernet/marvell/octeontx2/nic/ |
| H A D | otx2_ptp.c | 22 mutex_lock(&ptp->nic->mbox.lock); in is_tstmp_atomic_update_supported()
23 req = otx2_mbox_alloc_msg_ptp_get_cap(&ptp->nic->mbox); in is_tstmp_atomic_update_supported()
25 mutex_unlock(&ptp->nic->mbox.lock); in is_tstmp_atomic_update_supported()
29 err = otx2_sync_mbox_msg(&ptp->nic->mbox); in is_tstmp_atomic_update_supported()
31 mutex_unlock(&ptp->nic->mbox.lock); in is_tstmp_atomic_update_supported()
34 rsp = (struct ptp_get_cap_rsp *)otx2_mbox_get_rsp(&ptp->nic->mbox.mbox, 0, in is_tstmp_atomic_update_supported()
36 mutex_unlock(&ptp->nic->mbox.lock); in is_tstmp_atomic_update_supported()
58 mutex_lock(&pfvf->mbox.lock); in otx2_ptp_hw_adjtime()
59 req = otx2_mbox_alloc_msg_ptp_op(&ptp->nic->mbox); in otx2_ptp_hw_adjtime()
61 mutex_unlock(&pfvf->mbox.lock); in otx2_ptp_hw_adjtime()
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| /linux/drivers/net/wireless/ti/wl18xx/ |
| H A D | event.c | 118 struct wl18xx_event_mailbox *mbox = wl->mbox; in wl18xx_process_mailbox_events() local
121 vector = le32_to_cpu(mbox->events_vector); in wl18xx_process_mailbox_events()
122 wl1271_debug(DEBUG_EVENT, "MBOX vector: 0x%x", vector); in wl18xx_process_mailbox_events()
126 mbox->number_of_scan_results); in wl18xx_process_mailbox_events()
134 le16_to_cpu(mbox->time_sync_tsf_high_msb), in wl18xx_process_mailbox_events()
135 le16_to_cpu(mbox->time_sync_tsf_high_lsb), in wl18xx_process_mailbox_events()
136 le16_to_cpu(mbox->time_sync_tsf_low_msb), in wl18xx_process_mailbox_events()
137 le16_to_cpu(mbox->time_sync_tsf_low_lsb)); in wl18xx_process_mailbox_events()
141 mbox->radar_channel, in wl18xx_process_mailbox_events()
142 wl18xx_radar_type_decode(mbox->radar_type)); in wl18xx_process_mailbox_events()
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| /linux/drivers/net/wireless/ti/wl1251/ |
| H A D | event.c | 16 struct event_mailbox *mbox) in wl1251_event_scan_complete() argument
21 mbox->scheduled_scan_status, in wl1251_event_scan_complete()
22 mbox->scheduled_scan_channels); in wl1251_event_scan_complete()
41 struct event_mailbox *mbox) in wl1251_event_ps_report() argument
45 wl1251_debug(DEBUG_EVENT, "ps status: %x", mbox->ps_status); in wl1251_event_ps_report()
47 switch (mbox->ps_status) { in wl1251_event_ps_report()
76 static void wl1251_event_mbox_dump(struct event_mailbox *mbox) in wl1251_event_mbox_dump() argument
78 wl1251_debug(DEBUG_EVENT, "MBOX DUMP:"); in wl1251_event_mbox_dump()
79 wl1251_debug(DEBUG_EVENT, "\tvector: 0x%x", mbox->events_vector); in wl1251_event_mbox_dump()
80 wl1251_debug(DEBUG_EVENT, "\tmask: 0x%x", mbox->events_mask); in wl1251_event_mbox_dump()
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| /linux/drivers/gpu/drm/i915/ |
| H A D | intel_pcode.c | 10 static int gen6_check_mailbox_status(u32 mbox) in gen6_check_mailbox_status() argument
12 switch (mbox & GEN6_PCODE_ERROR_MASK) { in gen6_check_mailbox_status()
25 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK); in gen6_check_mailbox_status()
30 static int gen7_check_mailbox_status(u32 mbox) in gen7_check_mailbox_status() argument
32 switch (mbox & GEN6_PCODE_ERROR_MASK) { in gen7_check_mailbox_status()
50 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK); in gen7_check_mailbox_status()
55 static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox, in __snb_pcode_rw() argument
74 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); in __snb_pcode_rw()
81 &mbox)) in __snb_pcode_rw()
90 return gen7_check_mailbox_status(mbox); in __snb_pcode_rw()
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| /linux/drivers/rapidio/devices/ |
| H A D | tsi721.c | 39 "RIO Messaging MBOX Selection Mask (default: 0x0f = all)");
520 * Process Inbound Message interrupt for each MBOX in tsi721_irqhandler()
536 * Process Outbound Message interrupts for each MBOX in tsi721_irqhandler()
628 int mbox; in tsi721_omsg_msix() local
630 mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX; in tsi721_omsg_msix()
631 tsi721_omsg_handler(priv, mbox); in tsi721_omsg_msix()
647 int mbox; in tsi721_imsg_msix() local
649 mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX; in tsi721_imsg_msix()
650 tsi721_imsg_handler(priv, mbox + 4); in tsi721_imsg_msix()
757 * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore in tsi721_enable_msix()
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| /linux/drivers/scsi/lpfc/ |
| H A D | lpfc_mbox.c | 49 * @mbox: pointer to the driver internal queue element for mailbox command.
51 * A mailbox command consists of the pool memory for the command, @mbox, and
54 * @mbox. Callers should cleanup the mbox with a call to
59 * driver design is a single dmabuf/mbuf per mbox in the ctx_buf.
63 lpfc_mbox_rsrc_prep(struct lpfc_hba *phba, LPFC_MBOXQ_t *mbox) in lpfc_mbox_rsrc_prep() argument
81 mbox->ctx_buf = mp; in lpfc_mbox_rsrc_prep()
88 * @mbox: pointer to the driver internal queue element for mailbox command.
91 * A mailbox command consists of the pool memory for the command, @mbox, and
94 * memory resources in it as well as releasing the @mbox back to the @phba pool.
100 lpfc_mbox_rsrc_cleanup(struct lpfc_hba *phba, LPFC_MBOXQ_t *mbox, in lpfc_mbox_rsrc_cleanup() argument
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| /linux/drivers/infiniband/hw/mlx5/ |
| H A D | qpc.c | 341 static int mbox_alloc(struct mbox_info *mbox, int inlen, int outlen) in mbox_alloc() argument
343 mbox->inlen = inlen; in mbox_alloc()
344 mbox->outlen = outlen; in mbox_alloc()
345 mbox->in = kzalloc(mbox->inlen, GFP_KERNEL); in mbox_alloc()
346 mbox->out = kzalloc(mbox->outlen, GFP_KERNEL); in mbox_alloc()
347 if (!mbox->in || !mbox->out) { in mbox_alloc()
348 kfree(mbox->in); in mbox_alloc()
349 kfree(mbox->out); in mbox_alloc()
356 static void mbox_free(struct mbox_info *mbox) in mbox_free() argument
358 kfree(mbox->in); in mbox_free()
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