Searched +full:mbl +full:- +full:gpio (Results 1 – 2 of 2) sorted by relevance
1 Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.3 The Western Digital MyBook Live has two memory-mapped GPIO controllers.4 Both GPIO controller only have a single 8-bit data register, where GPIO8 - compatible: should be "wd,mbl-gpio"9 - reg-names: must contain10 "dat" - data register11 - reg: address + size pairs describing the GPIO register sets;12 order must correspond with the order of entries in reg-names13 - #gpio-cells: must be set to 2. The first cell is the pin number and14 the second cell is used to specify the gpio polarity:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Generic MMIO GPIO10 - Linus Walleij <linus.walleij@linaro.org>11 - Bartosz Golaszewski <brgl@bgdev.pl>14 Some simple GPIO controllers may consist of a single data register or a pair15 of set/clear-bit registers. Such controllers are common for glue logic in16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped[all …]