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Searched +full:max +full:- +full:pixelclock (Results 1 – 17 of 17) sorted by relevance

/linux/include/video/
H A Ddisplay_timing.h1 /* SPDX-License-Identifier: GPL-2.0-only */
43 u32 max; member
56 * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync..
64 struct timing_entry pixelclock; member
97 if (disp->num_timings > index) in display_timings_get()
98 return disp->timings[index]; in display_timings_get()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_core_structs.h1 /* SPDX-License-Identifier: MIT */
449 dml_float_t PixelClock; member
530 dml_uint_t GPUVMMaxPageTableLevels; /// <brief GPUVM level; max of all pipes'
531 …_t HostVMMaxPageTableLevels; /// <brief HostVM level; max of all pipes'; that is the number of non…
564 …SizeOverride[__DML_NUM_PLANES__]; /// <brief user can specify the desire DET buffer usage per-plane
609 dml_float_t PixelClock[__DML_NUM_PLANES__]; member
653 … as what the mode support stage derive. When call mode_support with mode_programm; the hw-specific
665 …r can select between use the min require clk req as calculated by DML or use the test-specific freq
666 …r can select between use the min require clk req as calculated by DML or use the test-specific freq
675 /// Describe how to display a surface in multi-plane setup and output to different output an…
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H A Ddml_display_rq_dlg_calc.c1 /* SPDX-License-Identifier: MIT */
44 …enum dml_source_format_class source_format = mode_lib->ms.cache_display_cfg.surface.SourcePixelFor… in dml_rq_dlg_get_rq_reg()
45 …enum dml_swizzle_mode sw_mode = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[plane_idx… in dml_rq_dlg_get_rq_reg()
97 rq_regs->rq_regs_l.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) pixel_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
98 rq_regs->rq_regs_c.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_pixel_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
101 rq_regs->rq_regs_l.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
103 …rq_regs->rq_regs_l.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) min_pixel_chunk_bytes) - 8… in dml_rq_dlg_get_rq_reg()
106 rq_regs->rq_regs_c.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
108 …rq_regs->rq_regs_c.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_min_pixel_chunk_bytes) … in dml_rq_dlg_get_rq_reg()
110 rq_regs->rq_regs_l.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) meta_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
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/linux/drivers/video/fbdev/core/
H A Dfbmon.c11 * Copyright (C) 1991-2002 SciTech Software, Inc. All rights reserved.
14 * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
67 /* DEC FR-PCXAV-YZ */
98 while (i-- && (*--s == 0x20)) *s = 0; in copy_string()
245 b[9] = 17; /* pixclock - 170 MHz*/ in fix_edid()
253 for (i = 0; i < EDID_LENGTH - 1; i++) in fix_edid()
256 edid[127] = 256 - csum; in fix_edid()
299 specs->manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@'; in parse_vendor_block()
300 specs->manufacturer[1] = ((block[0] & 0x03) << 3) + in parse_vendor_block()
302 specs->manufacturer[2] = (block[1] & 0x1f) + '@'; in parse_vendor_block()
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/linux/drivers/video/
H A Dof_display_timing.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * parse_timing_property - parse timing_entry from device_node
23 * a range consisting of min/typ/max. This function helps handling this
34 return -EINVAL; in parse_timing_property()
39 ret = of_property_read_u32(np, name, &result->typ); in parse_timing_property()
40 result->min = result->typ; in parse_timing_property()
41 result->max = result->typ; in parse_timing_property()
43 ret = of_property_read_u32_array(np, name, &result->min, cells); in parse_timing_property()
46 return -EINVAL; in parse_timing_property()
53 * of_parse_display_timing - parse display_timing entry from device_node
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/linux/drivers/gpu/drm/tilcdc/
H A Dtilcdc_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
7 /* LCDC DRM driver, based on da8xx-fb */
64 * tilcdc ->atomic_check can update ->mode_changed if pixel format in tilcdc_atomic_check()
84 dev->mode_config.min_width = 0; in modeset_init()
85 dev->mode_config.min_height = 0; in modeset_init()
86 dev->mode_config.max_width = priv->max_width; in modeset_init()
87 dev->mode_config.max_height = 2048; in modeset_init()
88 dev->mode_config.funcs = &mode_config_funcs; in modeset_init()
99 tilcdc_crtc_update_clk(priv->crtc); in cpufreq_transition()
110 return tilcdc_crtc_irq(priv->crtc); in tilcdc_irq()
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/linux/drivers/video/fbdev/via/
H A Ddvi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
7 #include <linux/via-core.h>
41 switch (viaparinfo->chip_info->gfx_chip_name) { in viafb_tmds_trasmitter_identify()
63 /* SR3E[1]Multi-function selection: in viafb_tmds_trasmitter_identify()
71 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS; in viafb_tmds_trasmitter_identify()
72 viaparinfo->chip_info-> in viafb_tmds_trasmitter_identify()
74 viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_31; in viafb_tmds_trasmitter_identify()
83 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name); in viafb_tmds_trasmitter_identify()
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/linux/drivers/gpu/drm/bridge/
H A Dinno-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Zheng Yang <zhengyang@rock-chips.com>
5 * Yakir Yang <ykk@rock-chips.com>
416 * Cb = -0.291G - 0.148R + 0.439B + 128
418 * Cr = -0.368G + 0.439R - 0.071B + 128
427 * Cb = - 0.338G - 0.101R + 0.439B + 128
429 * Cr = - 0.399G + 0.439R - 0.040B + 128
438 * R' = R x (235-16)/255 + 16;
439 * G' = G x (235-16)/255 + 16;
440 * B' = B x (235-16)/255 + 16;
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/linux/drivers/video/fbdev/omap2/omapfb/displays/
H A Dpanel-nec-nl8048hl11.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 * MIN:21.8MHz TYP:23.8MHz MAX:25.7MHz
67 .pixelclock = LCD_PIXEL_CLOCK,
106 for (i = 0; i < (ARRAY_SIZE(nec_8048_init_seq) - 1); i++) in init_nec_8048_wvga_lcd()
118 struct omap_dss_device *in = ddata->in; in nec_8048_connect()
123 return in->ops.dpi->connect(in, dssdev); in nec_8048_connect()
129 struct omap_dss_device *in = ddata->in; in nec_8048_disconnect()
134 in->ops.dpi->disconnect(in, dssdev); in nec_8048_disconnect()
140 struct omap_dss_device *in = ddata->in; in nec_8048_enable()
144 return -ENODEV; in nec_8048_enable()
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H A Dpanel-sony-acx565akm.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Based on panel-generic.c by Tomi Valkeinen <tomi.valkeinen@nokia.com>
75 unsigned long hw_guard_wait; /* max guard time in jiffies */
86 .pixelclock = 24000000,
111 BUG_ON(ddata->spi == NULL); in acx565akm_transfer()
119 x->tx_buf = &cmd; in acx565akm_transfer()
120 x->bits_per_wor in acx565akm_transfer()
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H A Dpanel-dsi-cm.c1 // SPDX-License-Identifier: GPL-2.0-only
52 unsigned long hw_guard_wait; /* max guard time in jiffies */
91 ddata->hw_guard_wait = msecs_to_jiffies(guard_msec); in hw_guard_start()
92 ddata->hw_guard_end = jiffies + ddata->hw_guard_wait; in hw_guard_start()
97 unsigned long wait = ddata->hw_guard_end - jiffies; in hw_guard_wait()
99 if ((long)wait > 0 && time_before_eq(wait, ddata->hw_guard_wait)) { in hw_guard_wait()
107 struct omap_dss_device *in = ddata->in; in dsicm_dcs_read_1()
111 r = in->ops.dsi->dcs_read(in, ddata->channel, dcs_cmd, buf, 1); in dsicm_dcs_read_1()
123 struct omap_dss_device *in = ddata->in; in dsicm_dcs_write_0()
124 return in->ops.dsi->dcs_write(in, ddata->channel, &dcs_cmd, 1); in dsicm_dcs_write_0()
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/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
176 /* maps which plane is using a fifo. fifo-id -> plane-id */
358 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
363 return __raw_readl(dispc->base + idx); in dispc_read_reg()
371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
384 return dispc->feat->num_ovls; in dispc_get_num_ovls()
389 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
396 BUG_ON(id >= dispc->feat->num_reg_fields); in dispc_get_reg_field()
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_hw.c1 // SPDX-License-Identifier: GPL-2.0-only
29 MW_ONESHOT, /* SE in one-shot mode for writeback */
196 [MALIDP_UPSCALING_COEFFS - 1] = {
210 [MALIDP_DOWNSCALING_1_5_COEFFS - 1] = {
224 [MALIDP_DOWNSCALING_2_COEFFS - 1] = {
238 [MALIDP_DOWNSCALING_2_75_COEFFS - 1] = {
252 [MALIDP_DOWNSCALING_4_COEFFS - 1] = {
276 hwdev->min_line_size = 2; in malidp500_query_hw()
277 hwdev->max_line_size = SZ_2K * ln_size_mult; in malidp500_query_hw()
278 hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult; in malidp500_query_hw()
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/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c342 -1270850L,
624 -1270850L,
1116 -1270850L,
1643 -1270850L,
1674 -1270850L,
1825 -1270850L,
1870 struct si_power_info *pi = adev->pm.dpm.priv; in si_get_pi()
1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000); in si_calculate_leakage_for_v_and_t_formula()
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