| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
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| H A D | snps,dw-axi-dmac.txt | 4 - compatible: "snps,axi-dma-1.01a"
5 - reg: Address range of the DMAC registers. This should include
6 all of the per-channel registers.
7 - interrupt: Should contain the DMAC interrupt number.
8 - dma-channels: Number of channels supported by hardware.
9 - snps,dma-masters: Number of AXI masters supported by the hardware.
10 - snps,data-width: Maximum AXI data width supported by hardware.
11 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
12 - snps,priority: Priority of channel. Array size is equal to the number of
13 dma-channels. Priority value must be programmed within [0:dma-channels-1]
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| H A D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
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| H A D | snps,dw-axi-dmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
24 - starfive,jh8100-axi-dma
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| H A D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | snps,dwc3-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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| H A D | dwc3.txt | 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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| H A D | ci-hdrc-usb2.txt | 4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
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| H A D | chipidea,usb2-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
48 itc-setting:
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_config.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
81 uint8_t burst; member
94 al_bool break_on_max_boundary; /* Data read break on max boundary */
95 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
107 al_bool break_on_max_boundary; /* Data read break on max boundary */
108 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
114 uint8_t ack_fifo_depth; /* size of the stream application ack fifo */
123 /** M2S max packet size configuration */
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | samsung-sxgbe.txt | 4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Lengt
[all...] |
| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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| H A D | qca,qca7000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The QCA7000 is a serial-to-powerline bridge with a host interface which could
39 qca,legacy-mode:
44 between each data word. In burst mode these gaps aren't
47 property is missing the driver defaults to burst mode.
50 - $ref: ethernet-controller.yaml#
52 - if:
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| /freebsd/sys/netinet/ |
| H A D | sctp_sysctl.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2008-2012, by Randall Stewart. All rights reserved.
6 * Copyright (c) 2008-2012, by Michael Tuexen. All rights reserved.
93 /* JRS - Variable for default congestion control module */
95 /* RS - Variable for default stream scheduling module */
126 /* maxdgram: Maximum outgoing SCTP buffer size */
127 #define SCTPCTL_MAXDGRAM_DESC "Maximum outgoing SCTP buffer size"
132 /* recvspace: Maximum incoming SCTP buffer size */
133 #define SCTPCTL_RECVSPACE_DESC "Maximum incoming SCTP buffer size"
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| /freebsd/share/man/man4/ |
| H A D | sctp.4 | 47 protocol provides reliable, flow-controlled, two-way
57 Internet address format and, in addition, provides a per-host
105 third leg of the four-way handshake.
116 protocol directly supports multi-homing.
129 transport protocol is also multi-streamed.
130 Multi-streaming refers to the ability to send sub-ordered flows of
159 .Bl -tag -width "sctp partial reliability"
172 so that two stacks can pre-share keys.
190 .Bl -tag -width indent
217 For the one-to-many model
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6qdl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
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| H A D | imx6sl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
51 #size-cells = <0>;
54 compatible = "arm,cortex-a9";
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,coresight-tmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
32 const: arm,coresight-tmc
34 - compatible
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| /freebsd/sys/dev/mlx5/mlx5_en/ |
| H A D | en_rl.h | 1 /*-
50 #define MLX5E_RL_WORKER_LOCK(rlw) mtx_lock(&(rlw)->mtx)
51 #define MLX5E_RL_WORKER_UNLOCK(rlw) mtx_unlock(&(rlw)->mtx)
53 #define MLX5E_RL_RLOCK(rl) sx_slock(&(rl)->rl_sxlock)
54 #define MLX5E_RL_RUNLOCK(rl) sx_sunlock(&(rl)->rl_sxlock)
56 #define MLX5E_RL_WLOCK(rl) sx_xlock(&(rl)->rl_sxlock)
57 #define MLX5E_RL_WUNLOCK(rl) sx_xunlock(&(rl)->rl_sxlock)
60 m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \
64 m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
66 m(+1, u64, tx_worker_threads_max, "tx_worker_threads_max", "Max number of TX worker threads") \
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| H A D | mlx5_en_rl.c | 1 /*-
2 * Copyright (c) 2016-2020 Mellanox Technologies. All rights reserved.
57 void *sqc = param->sqc; in mlx5e_rl_build_sq_param()
59 uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size); in mlx5e_rl_build_sq_param()
63 MLX5_SET(wq, wq, pd, rl->priv->pdn); in mlx5e_rl_build_sq_param()
65 param->wq.linear = 1; in mlx5e_rl_build_sq_param()
72 void *cqc = param->cqc; in mlx5e_rl_build_cq_param()
73 uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size); in mlx5e_rl_build_cq_param()
76 MLX5_SET(cqc, cqc, cq_period, rl->param.tx_coalesce_usecs); in mlx5e_rl_build_cq_param()
77 MLX5_SET(cqc, cqc, cq_max_count, rl->param.tx_coalesce_pkts); in mlx5e_rl_build_cq_param()
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap3-n950-n9.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
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| /freebsd/sys/kern/ |
| H A D | kern_poll.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2002 Luigi Rizzo
74 * call -- typically this is the number of packets to be received, or
76 * as the max time spent in the function grows roughly linearly with the
106 SYSCTL_UINT(_kern_polling, OID_AUTO, burst, CTLFLAG_RD,
107 &poll_burst, 0, "Current polling burst size");
119 if (error || !req->newptr ) in poll_burst_max_sysctl()
137 "Max Polling burst size");
145 if (error || !req->newptr ) in poll_each_burst_sysctl()
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| /titanic_41/usr/src/man/man9s/ |
| H A D | ddi_dma_attr.9s | 8 ddi_dma_attr \- DMA attributes structure
22 A \fBddi_dma_attr_t\fR structure describes device- and \fBDMA\fR
23 engine-specific attributes necessary to allocate \fBDMA\fR resources for a
24 device. The driver might have to extend the attributes with bus-specific
36 uint32_t dma_attr_minxfer; /* min effective DMA size */
37 uint64_t dma_attr_maxxfer; /* max DMA xfer size */
54 \fBdma_attr_addr_lo\fR field describes the inclusive lower 64-bit boundary. The
55 \fBdma_attr_addr_hi\fR describes the inclusive upper 64-bit boundary. The
62 a \fBDMA\fR engine with a 24-bit counter register. \fBDMA\fR resource
64 \fBDMA\fR cookies if the size of the object exceeds the size of the \fBDMA\fR
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| /titanic_41/usr/src/uts/common/io/hme/ |
| H A D | hme_mac.h | 32 /* The pointers to the Descriptor Ring base Addresses must be 2K-byte aligned */
37 * The transmit and receiver Descriptor Rings are organized as "wrap-around
38 * descriptors of programmable size.
40 #define HME_TMDMAX (64) /* Transmit descriptor ring size */
41 #define HME_RMDMAX (64) /* Receive descriptor ring size */
47 uint_t tmd_addr; /* 8-bye aligned buffer address */
52 #define HMETMD_BUFSIZE (0x3fff << 0) /* 0-13 : Tx Data buffer size */
53 #define HMETMD_CSSTART (0x3f << 14) /* 14-19 : Checksum start offset */
54 #define HMETMD_CSSTUFF (0xff << 20) /* 20-27 : Checksum stuff offset */
59 /* 0 - owned by software */
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| /titanic_41/usr/src/uts/common/io/ib/clients/rdsv3/ |
| H A D | rdsv3_debug.c | 35 * messages with level lower than rdsv3dbglvl are ignored. The size of the
48 #define RDSV3_DEBUG_BUF_SIZE 0x200000 /* 2M size */
53 /* Max length of a debug statement */
90 rdsv3_debug_buf_size = max(RDSV3_MIN_DEBUG_BUF_SIZE, in rdsv3_logging_initialization()
131 rdsv3_buf_eptr = rdsv3_debug_buf + rdsv3_debug_buf_size - in rdsv3_clear_print_buf()
166 len += vsnprintf(msg_ptr, RDSV3_PRINT_BUF_LEN - len - 2, fmt, ap); in rdsv3_vlog()
168 len = min(len, RDSV3_PRINT_BUF_LEN - 2); in rdsv3_vlog()
185 size_t left = (uintptr_t)rdsv3_buf_eptr - in rdsv3_vlog()
191 (caddr_t)rdsv3_debug_buf, len - left); in rdsv3_vlog()
192 rdsv3_buf_sptr = rdsv3_debug_buf + len - left; in rdsv3_vlog()
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