1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - qcom,sdm630-smmu-v2 32 - qcom,sm6375-smmu-v2 33 - const: qcom,smmu-v2 34 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" 36 items: 37 - enum: 38 - qcom,milos-smmu-500 39 - qcom,qcm2290-smmu-500 40 - qcom,qcs615-smmu-500 41 - qcom,qcs8300-smmu-500 42 - qcom,qdu1000-smmu-500 43 - qcom,sa8255p-smmu-500 44 - qcom,sa8775p-smmu-500 45 - qcom,sar2130p-smmu-500 46 - qcom,sc7180-smmu-500 47 - qcom,sc7280-smmu-500 48 - qcom,sc8180x-smmu-500 49 - qcom,sc8280xp-smmu-500 50 - qcom,sdm670-smmu-500 51 - qcom,sdm845-smmu-500 52 - qcom,sdx55-smmu-500 53 - qcom,sdx65-smmu-500 54 - qcom,sdx75-smmu-500 55 - qcom,sm6115-smmu-500 56 - qcom,sm6125-smmu-500 57 - qcom,sm6350-smmu-500 58 - qcom,sm6375-smmu-500 59 - qcom,sm8150-smmu-500 60 - qcom,sm8250-smmu-500 61 - qcom,sm8350-smmu-500 62 - qcom,sm8450-smmu-500 63 - qcom,sm8550-smmu-500 64 - qcom,sm8650-smmu-500 65 - qcom,sm8750-smmu-500 66 - qcom,x1e80100-smmu-500 67 - const: qcom,smmu-500 68 - const: arm,mmu-500 69 70 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) 71 deprecated: true 72 items: 73 # Do not add additional SoC to this list. Instead use two previous lists. 74 - enum: 75 - qcom,qcm2290-smmu-500 76 - qcom,sc7180-smmu-500 77 - qcom,sc7280-smmu-500 78 - qcom,sc8180x-smmu-500 79 - qcom,sc8280xp-smmu-500 80 - qcom,sdm845-smmu-500 81 - qcom,sm6115-smmu-500 82 - qcom,sm6350-smmu-500 83 - qcom,sm6375-smmu-500 84 - qcom,sm8150-smmu-500 85 - qcom,sm8250-smmu-500 86 - qcom,sm8350-smmu-500 87 - qcom,sm8450-smmu-500 88 - const: arm,mmu-500 89 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" 90 items: 91 - enum: 92 - qcom,milos-smmu-500 93 - qcom,qcm2290-smmu-500 94 - qcom,qcs615-smmu-500 95 - qcom,qcs8300-smmu-500 96 - qcom,sa8255p-smmu-500 97 - qcom,sa8775p-smmu-500 98 - qcom,sar2130p-smmu-500 99 - qcom,sc7280-smmu-500 100 - qcom,sc8180x-smmu-500 101 - qcom,sc8280xp-smmu-500 102 - qcom,sm6115-smmu-500 103 - qcom,sm6125-smmu-500 104 - qcom,sm8150-smmu-500 105 - qcom,sm8250-smmu-500 106 - qcom,sm8350-smmu-500 107 - qcom,sm8450-smmu-500 108 - qcom,sm8550-smmu-500 109 - qcom,sm8650-smmu-500 110 - qcom,sm8750-smmu-500 111 - qcom,x1e80100-smmu-500 112 - const: qcom,adreno-smmu 113 - const: qcom,smmu-500 114 - const: arm,mmu-500 115 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) 116 deprecated: true 117 items: 118 # Do not add additional SoC to this list. Instead use previous list. 119 - enum: 120 - qcom,sc7280-smmu-500 121 - qcom,sm8150-smmu-500 122 - qcom,sm8250-smmu-500 123 - const: qcom,adreno-smmu 124 - const: arm,mmu-500 125 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 126 items: 127 - enum: 128 - qcom,msm8996-smmu-v2 129 - qcom,sc7180-smmu-v2 130 - qcom,sdm630-smmu-v2 131 - qcom,sdm670-smmu-v2 132 - qcom,sdm845-smmu-v2 133 - qcom,sm6350-smmu-v2 134 - qcom,sm7150-smmu-v2 135 - const: qcom,adreno-smmu 136 - const: qcom,smmu-v2 137 - description: Marvell SoCs implementing "arm,mmu-500" 138 items: 139 - const: marvell,ap806-smmu-500 140 - const: arm,mmu-500 141 - description: NVIDIA SoCs that require memory controller interaction 142 and may program multiple ARM MMU-500s identically with the memory 143 controller interleaving translations between multiple instances 144 for improved performance. 145 items: 146 - enum: 147 - nvidia,tegra186-smmu 148 - nvidia,tegra194-smmu 149 - nvidia,tegra234-smmu 150 - const: nvidia,smmu-500 151 - items: 152 - const: arm,mmu-500 153 - const: arm,smmu-v2 154 - items: 155 - enum: 156 - arm,mmu-400 157 - arm,mmu-401 158 - const: arm,smmu-v1 159 - enum: 160 - arm,smmu-v1 161 - arm,smmu-v2 162 - arm,mmu-400 163 - arm,mmu-401 164 - arm,mmu-500 165 - cavium,smmu-v2 166 167 reg: 168 minItems: 1 169 maxItems: 2 170 171 '#global-interrupts': 172 description: The number of global interrupts exposed by the device. 173 $ref: /schemas/types.yaml#/definitions/uint32 174 minimum: 0 175 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 176 177 '#iommu-cells': 178 enum: [ 1, 2 ] 179 description: | 180 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 181 value of 1, each IOMMU specifier represents a distinct stream ID emitted 182 by that device into the relevant SMMU. 183 184 SMMUs with stream matching support and complex masters may use a value of 185 2, where the second cell of the IOMMU specifier represents an SMR mask to 186 combine with the ID in the first cell. Care must be taken to ensure the 187 set of matched IDs does not result in conflicts. 188 189 interrupts: 190 minItems: 1 191 maxItems: 388 # 260 plus 128 contexts 192 description: | 193 Interrupt list, with the first #global-interrupts entries corresponding to 194 the global interrupts and any following entries corresponding to context 195 interrupts, specified in order of their indexing by the SMMU. 196 197 For SMMUv2 implementations, there must be exactly one interrupt per 198 context bank. In the case of a single, combined interrupt, it must be 199 listed multiple times. 200 201 dma-coherent: 202 description: | 203 Present if page table walks made by the SMMU are cache coherent with the 204 CPU. 205 206 NOTE: this only applies to the SMMU itself, not masters connected 207 upstream of the SMMU. 208 209 calxeda,smmu-secure-config-access: 210 type: boolean 211 description: 212 Enable proper handling of buggy implementations that always use secure 213 access to SMMU configuration registers. In this case non-secure aliases of 214 secure registers have to be used during SMMU configuration. 215 216 stream-match-mask: 217 $ref: /schemas/types.yaml#/definitions/uint32 218 description: | 219 For SMMUs supporting stream matching and using #iommu-cells = <1>, 220 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 221 be programmed into the SMRn.MASK field of every stream match register 222 used). For cases where it is desirable to ignore some portion of every 223 Stream ID (e.g. for certain MMU-500 configurations given globally unique 224 input IDs). This property is not valid for SMMUs using stream indexing, or 225 using stream matching with #iommu-cells = <2>, and may be ignored if 226 present in such cases. 227 228 clock-names: 229 minItems: 1 230 maxItems: 7 231 232 clocks: 233 minItems: 1 234 maxItems: 7 235 236 power-domains: 237 minItems: 1 238 maxItems: 3 239 240 nvidia,memory-controller: 241 description: | 242 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 243 The memory controller needs to be programmed with a mapping of memory 244 client IDs to ARM SMMU stream IDs. 245 246 If this property is absent, the mapping programmed by early firmware 247 will be used and it is not guaranteed that IOMMU translations will be 248 enabled for any given device. 249 $ref: /schemas/types.yaml#/definitions/phandle 250 251required: 252 - compatible 253 - reg 254 - '#global-interrupts' 255 - '#iommu-cells' 256 - interrupts 257 258additionalProperties: false 259 260allOf: 261 - if: 262 properties: 263 compatible: 264 contains: 265 enum: 266 - nvidia,tegra186-smmu 267 - nvidia,tegra194-smmu 268 - nvidia,tegra234-smmu 269 then: 270 properties: 271 reg: 272 minItems: 1 273 maxItems: 2 274 275 # The reference to the memory controller is required to ensure that the 276 # memory client to stream ID mapping can be done synchronously with the 277 # IOMMU attachment. 278 required: 279 - nvidia,memory-controller 280 else: 281 properties: 282 reg: 283 maxItems: 1 284 285 - if: 286 properties: 287 compatible: 288 contains: 289 enum: 290 - qcom,msm8998-smmu-v2 291 - qcom,sdm630-smmu-v2 292 then: 293 anyOf: 294 - properties: 295 clock-names: 296 items: 297 - const: bus 298 clocks: 299 items: 300 - description: bus clock required for downstream bus access and for 301 the smmu ptw 302 - properties: 303 clock-names: 304 items: 305 - const: iface 306 - const: mem 307 - const: mem_iface 308 clocks: 309 items: 310 - description: interface clock required to access smmu's registers 311 through the TCU's programming interface. 312 - description: bus clock required for memory access 313 - description: bus clock required for GPU memory access 314 - properties: 315 clock-names: 316 items: 317 - const: iface-mm 318 - const: iface-smmu 319 - const: bus-smmu 320 clocks: 321 items: 322 - description: interface clock required to access mnoc's registers 323 through the TCU's programming interface. 324 - description: interface clock required to access smmu's registers 325 through the TCU's programming interface. 326 - description: bus clock required for the smmu ptw 327 328 - if: 329 properties: 330 compatible: 331 contains: 332 enum: 333 - qcom,sm6375-smmu-v2 334 then: 335 anyOf: 336 - properties: 337 clock-names: 338 items: 339 - const: bus 340 clocks: 341 items: 342 - description: bus clock required for downstream bus access and for 343 the smmu ptw 344 - properties: 345 clock-names: 346 items: 347 - const: iface 348 - const: mem 349 - const: mem_iface 350 clocks: 351 items: 352 - description: interface clock required to access smmu's registers 353 through the TCU's programming interface. 354 - description: bus clock required for memory access 355 - description: bus clock required for GPU memory access 356 - properties: 357 clock-names: 358 items: 359 - const: iface-mm 360 - const: iface-smmu 361 - const: bus-mm 362 - const: bus-smmu 363 clocks: 364 items: 365 - description: interface clock required to access mnoc's registers 366 through the TCU's programming interface. 367 - description: interface clock required to access smmu's registers 368 through the TCU's programming interface. 369 - description: bus clock required for downstream bus access 370 - description: bus clock required for the smmu ptw 371 372 - if: 373 properties: 374 compatible: 375 contains: 376 enum: 377 - qcom,msm8996-smmu-v2 378 - qcom,sc7180-smmu-v2 379 - qcom,sdm845-smmu-v2 380 then: 381 properties: 382 clock-names: 383 items: 384 - const: bus 385 - const: iface 386 387 clocks: 388 items: 389 - description: bus clock required for downstream bus access and for 390 the smmu ptw 391 - description: interface clock required to access smmu's registers 392 through the TCU's programming interface. 393 394 - if: 395 properties: 396 compatible: 397 contains: 398 enum: 399 - qcom,qcs8300-smmu-500 400 - qcom,sa8775p-smmu-500 401 - qcom,sc7280-smmu-500 402 - qcom,sc8280xp-smmu-500 403 then: 404 properties: 405 clock-names: 406 items: 407 - const: gcc_gpu_memnoc_gfx_clk 408 - const: gcc_gpu_snoc_dvm_gfx_clk 409 - const: gpu_cc_ahb_clk 410 - const: gpu_cc_hlos1_vote_gpu_smmu_clk 411 - const: gpu_cc_cx_gmu_clk 412 - const: gpu_cc_hub_cx_int_clk 413 - const: gpu_cc_hub_aon_clk 414 415 clocks: 416 items: 417 - description: GPU memnoc_gfx clock 418 - description: GPU snoc_dvm_gfx clock 419 - description: GPU ahb clock 420 - description: GPU hlos1_vote_GPU smmu clock 421 - description: GPU cx_gmu clock 422 - description: GPU hub_cx_int clock 423 - description: GPU hub_aon clock 424 425 - if: 426 properties: 427 compatible: 428 contains: 429 enum: 430 - qcom,sc8180x-smmu-500 431 - qcom,sm6350-smmu-v2 432 - qcom,sm7150-smmu-v2 433 - qcom,sm8150-smmu-500 434 - qcom,sm8250-smmu-500 435 then: 436 properties: 437 clock-names: 438 items: 439 - const: ahb 440 - const: bus 441 - const: iface 442 443 clocks: 444 items: 445 - description: bus clock required for AHB bus access 446 - description: bus clock required for downstream bus access and for 447 the smmu ptw 448 - description: interface clock required to access smmu's registers 449 through the TCU's programming interface. 450 451 - if: 452 properties: 453 compatible: 454 items: 455 - enum: 456 - qcom,sm8350-smmu-500 457 - const: qcom,adreno-smmu 458 - const: qcom,smmu-500 459 - const: arm,mmu-500 460 then: 461 properties: 462 clock-names: 463 items: 464 - const: bus 465 - const: iface 466 - const: ahb 467 - const: hlos1_vote_gpu_smmu 468 - const: cx_gmu 469 - const: hub_cx_int 470 - const: hub_aon 471 clocks: 472 minItems: 7 473 maxItems: 7 474 475 - if: 476 properties: 477 compatible: 478 items: 479 - enum: 480 - qcom,qcm2290-smmu-500 481 - qcom,qcs615-smmu-500 482 - qcom,sm6115-smmu-500 483 - qcom,sm6125-smmu-500 484 - const: qcom,adreno-smmu 485 - const: qcom,smmu-500 486 - const: arm,mmu-500 487 then: 488 properties: 489 clock-names: 490 items: 491 - const: mem 492 - const: hlos 493 - const: iface 494 495 clocks: 496 items: 497 - description: GPU memory bus clock 498 - description: Voter clock required for HLOS SMMU access 499 - description: Interface clock required for register access 500 501 - if: 502 properties: 503 compatible: 504 items: 505 - const: qcom,sm8450-smmu-500 506 - const: qcom,adreno-smmu 507 - const: qcom,smmu-500 508 - const: arm,mmu-500 509 510 then: 511 properties: 512 clock-names: 513 items: 514 - const: gmu 515 - const: hub 516 - const: hlos 517 - const: bus 518 - const: iface 519 - const: ahb 520 521 clocks: 522 items: 523 - description: GMU clock 524 - description: GPU HUB clock 525 - description: HLOS vote clock 526 - description: GPU memory bus clock 527 - description: GPU SNoC bus clock 528 - description: GPU AHB clock 529 530 - if: 531 properties: 532 compatible: 533 items: 534 - enum: 535 - qcom,milos-smmu-500 536 - qcom,sar2130p-smmu-500 537 - qcom,sm8550-smmu-500 538 - qcom,sm8650-smmu-500 539 - qcom,x1e80100-smmu-500 540 - const: qcom,adreno-smmu 541 - const: qcom,smmu-500 542 - const: arm,mmu-500 543 then: 544 properties: 545 clock-names: 546 items: 547 - const: hlos 548 - const: bus 549 - const: iface 550 - const: ahb 551 552 clocks: 553 items: 554 - description: HLOS vote clock 555 - description: GPU memory bus clock 556 - description: GPU SNoC bus clock 557 - description: GPU AHB clock 558 559 - if: 560 properties: 561 compatible: 562 items: 563 - const: qcom,sm8750-smmu-500 564 - const: qcom,adreno-smmu 565 - const: qcom,smmu-500 566 - const: arm,mmu-500 567 then: 568 properties: 569 clock-names: 570 items: 571 - const: hlos 572 clocks: 573 items: 574 - description: HLOS vote clock 575 576 # Disallow clocks for all other platforms with specific compatibles 577 - if: 578 properties: 579 compatible: 580 contains: 581 enum: 582 - cavium,smmu-v2 583 - marvell,ap806-smmu-500 584 - nvidia,smmu-500 585 - qcom,qdu1000-smmu-500 586 - qcom,sa8255p-smmu-500 587 - qcom,sc7180-smmu-500 588 - qcom,sdm670-smmu-500 589 - qcom,sdm845-smmu-500 590 - qcom,sdx55-smmu-500 591 - qcom,sdx65-smmu-500 592 - qcom,sm6350-smmu-500 593 - qcom,sm6375-smmu-500 594 then: 595 properties: 596 clock-names: false 597 clocks: false 598 599 - if: 600 properties: 601 compatible: 602 contains: 603 const: qcom,sm6375-smmu-500 604 then: 605 properties: 606 power-domains: 607 items: 608 - description: SNoC MMU TBU RT GDSC 609 - description: SNoC MMU TBU NRT GDSC 610 - description: SNoC TURING MMU TBU0 GDSC 611 612 required: 613 - power-domains 614 else: 615 properties: 616 power-domains: 617 maxItems: 1 618 619examples: 620 - |+ 621 /* SMMU with stream matching or stream indexing */ 622 smmu1: iommu@ba5e0000 { 623 compatible = "arm,smmu-v1"; 624 reg = <0xba5e0000 0x10000>; 625 #global-interrupts = <2>; 626 interrupts = <0 32 4>, 627 <0 33 4>, 628 <0 34 4>, /* This is the first context interrupt */ 629 <0 35 4>, 630 <0 36 4>, 631 <0 37 4>; 632 #iommu-cells = <1>; 633 }; 634 635 /* device with two stream IDs, 0 and 7 */ 636 master1 { 637 iommus = <&smmu1 0>, 638 <&smmu1 7>; 639 }; 640 641 642 /* SMMU with stream matching */ 643 smmu2: iommu@ba5f0000 { 644 compatible = "arm,smmu-v1"; 645 reg = <0xba5f0000 0x10000>; 646 #global-interrupts = <2>; 647 interrupts = <0 38 4>, 648 <0 39 4>, 649 <0 40 4>, /* This is the first context interrupt */ 650 <0 41 4>, 651 <0 42 4>, 652 <0 43 4>; 653 #iommu-cells = <2>; 654 }; 655 656 /* device with stream IDs 0 and 7 */ 657 master2 { 658 iommus = <&smmu2 0 0>, 659 <&smmu2 7 0>; 660 }; 661 662 /* device with stream IDs 1, 17, 33 and 49 */ 663 master3 { 664 iommus = <&smmu2 1 0x30>; 665 }; 666 667 668 /* ARM MMU-500 with 10-bit stream ID input configuration */ 669 smmu3: iommu@ba600000 { 670 compatible = "arm,mmu-500", "arm,smmu-v2"; 671 reg = <0xba600000 0x10000>; 672 #global-interrupts = <2>; 673 interrupts = <0 44 4>, 674 <0 45 4>, 675 <0 46 4>, /* This is the first context interrupt */ 676 <0 47 4>, 677 <0 48 4>, 678 <0 49 4>; 679 #iommu-cells = <1>; 680 /* always ignore appended 5-bit TBU number */ 681 stream-match-mask = <0x7c00>; 682 }; 683 684 bus { 685 /* bus whose child devices emit one unique 10-bit stream 686 ID each, but may master through multiple SMMU TBUs */ 687 iommu-map = <0 &smmu3 0 0x400>; 688 689 690 }; 691 692 - |+ 693 /* Qcom's arm,smmu-v2 implementation */ 694 #include <dt-bindings/interrupt-controller/arm-gic.h> 695 #include <dt-bindings/interrupt-controller/irq.h> 696 smmu4: iommu@d00000 { 697 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 698 reg = <0xd00000 0x10000>; 699 700 #global-interrupts = <1>; 701 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 704 #iommu-cells = <1>; 705 power-domains = <&mmcc 0>; 706 707 clocks = <&mmcc 123>, 708 <&mmcc 124>; 709 clock-names = "bus", "iface"; 710 }; 711