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/linux/Documentation/devicetree/bindings/display/
H A Ddsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for DSI Display Panels
10 - Linus Walleij <linus.walleij@linaro.org>
13 This document defines device tree properties common to DSI, Display
22 Notice: this binding concerns DSI panels connected directly to a master
23 without any intermediate port graph to the panel. Each DSI master
26 reg-property set to the virtual channel number, usually there is just
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H A Dmipi-dsi-bus.txt1 MIPI DSI (Display Serial Interface) busses
6 define the syntax used to represent a DSI bus in a device tree.
8 This document describes DSI bus-specific properties only or defines existing
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
15 The following assumes that only a single peripheral is connected to a DSI
18 DSI host
22 a DSI host, the following properties apply to a node representing a DSI host.
25 - #address-cells: The number of cells required to represent an address on the
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
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H A Dtruly,nt35597.txt1 Truly model NT35597 DSI display driver
7 - compatible: should be "truly,nt35597-2K-display"
8 - vdda-supply: phandle of the regulator that provides the supply voltage
10 - vdispp-supply: phandle of the regulator that provides the supply voltage
12 - vdispn-supply: phandle of the regulator that provides the supply voltage
14 - reset-gpios: phandle of gpio for reset line
15 This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
17 - mode-gpios: phandle of the gpio for choosing the mode of the display
18 for single DSI or Dual DSI
19 This should be low for dual DSI and high for single DSI mode
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/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_manager.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "dsi.h"
18 * DSI_1 as master encoder
24 struct msm_dsi *dsi[DSI_MAX]; member
39 return msm_dsim_glb.dsi[id]; in dsi_mgr_get_dsi()
44 return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; in dsi_mgr_get_other_dsi()
51 /* We assume 2 dsi nodes have the same information of bonded dsi and in dsi_mgr_parse_of()
52 * sync-mode, and only one node specifies master in case of bonded mode. in dsi_mgr_parse_of()
54 if (!msm_dsim->is_bonded_dsi) in dsi_mgr_parse_of()
55 msm_dsim->is_bonded_dsi = of_property_read_bool(np, "qcom,dual-dsi-mode"); in dsi_mgr_parse_of()
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H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "dsi.h"
10 unsigned long host_flags = msm_dsi_host_get_mode_flags(msm_dsi->host); in msm_dsi_is_cmd_mode()
17 return msm_dsi_host_get_dsc_config(msm_dsi->host); in msm_dsi_get_dsc_config()
22 return msm_dsi_host_is_wide_bus_enabled(msm_dsi->host); in msm_dsi_wide_bus_enabled()
27 struct platform_device *pdev = msm_dsi->pdev; in dsi_get_phy()
31 phy_node = of_parse_phandle(pdev->dev.of_node, "phys", 0); in dsi_get_phy()
33 DRM_DEV_ERROR(&pdev->dev, "cannot find phy device\n"); in dsi_get_phy()
34 return -ENXIO; in dsi_get_phy()
39 msm_dsi->phy = platform_get_drvdata(phy_pdev); in dsi_get_phy()
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/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <drm/bridge/samsung-dsim.h>
27 struct exynos_dsi *dsi = dsim->priv; in exynos_dsi_te_irq_handler() local
28 struct drm_encoder *encoder = &dsi->encoder; in exynos_dsi_te_irq_handler()
30 if (dsim->state & DSIM_STATE_VIDOUT_AVAILABLE) in exynos_dsi_te_irq_handler()
31 exynos_drm_crtc_te_handler(encoder->crtc); in exynos_dsi_te_irq_handler()
39 struct exynos_dsi *dsi = dsim->priv; in exynos_dsi_host_attach() local
40 struct drm_encoder *encoder = &dsi->encoder; in exynos_dsi_host_attach()
41 struct drm_device *drm = encoder->dev; in exynos_dsi_host_attach()
43 drm_bridge_attach(encoder, &dsim->bridge, in exynos_dsi_host_attach()
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
16 #include <linux/media-bus-format.h>
196 #define N_LANES(n) (((n) - 1) & 0x3)
229 #define VPG_DEFS(name, dsi) \ argument
230 ((void __force *)&((*dsi).vpg_defs.name))
232 #define REGISTER(name, mask, dsi) \ argument
233 { #name, VPG_DEFS(name, dsi), mask, dsi }
239 struct dw_mipi_dsi *dsi; member
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/linux/drivers/gpu/drm/tegra/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
81 /* for ganged-mode support */
82 struct tegra_dsi *master; member
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
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/linux/drivers/gpu/drm/
H A Ddrm_of.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/media-bus-format.h>
25 * drm_of_crtc_port_mask - find the mask of a registered CRTC by port OF node
39 if (tmp->port == port) in drm_of_crtc_port_mask()
50 * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
83 * drm_of_component_match_add - Add a component helper OF node match rule
84 * @master: master device
89 void drm_of_component_match_add(struct device *master, in drm_of_component_match_add() argument
95 component_match_add_release(master, matchptr, component_release_of, in drm_of_component_match_add()
101 * drm_of_component_probe - Generic probe function for a component based master
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/linux/drivers/gpu/drm/rockchip/
H A Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
274 /* dual-channel */
365 return -EINVAL; in max_mbps_to_parameter()
368 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
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/linux/drivers/gpu/drm/msm/
H A DNOTES5 + MDP3 - ?? seems to be what is on geeksphone peak device
6 + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
7 + MDP5 - snapdragon 800
12 Plus a handful of blocks around them for HDMI/DSI/etc output.
18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple
20 with N different kms devices from xf86-video-freedreno. Plus, it
27 And one or more 'struct msm_gpu' for the various different gpu sub-
38 plane -> PIPE{RGBn,VGn} \
39 crtc -> OVLP{n} + DMA{P,S,E} (??) |-> MDP "device"
40 encoder -> DTV/LCDC/DSI (within MDP4) /
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/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-controller-main.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
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/linux/Documentation/devicetree/bindings/display/sprd/
H A Dsprd,display-subsystem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Unisoc DRM master device
10 - Kevin Tang <kevin.tang@unisoc.com>
13 The Unisoc DRM master device is a virtual device needed to list all
23 dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
24 dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
26 +-----------------------------------------+
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/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_combo_phy.c1 // SPDX-License-Identifier: MIT
17 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
33 .name = "0.85V dot0 (low-voltage)",
85 (0xff << 16) | 0xff, procmon->dw1); in icl_set_procmon_ref_values()
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
88 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
98 drm_dbg(&dev_priv->drm, in check_phy_reg()
118 (0xff << 16) | 0xff, procmon->dw1); in icl_verify_procmon_ref_values()
120 -1U, procmon->dw9); in icl_verify_procmon_ref_values()
122 -1U, procmon->dw10); in icl_verify_procmon_ref_values()
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/linux/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 HiSilicon Limited.
98 struct dw_dsi dsi; member
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
155 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
156 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
157 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
191 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
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/linux/drivers/gpu/drm/bridge/
H A Dtc358762.c1 // SPDX-License-Identifier: GPL-2.0
39 /* DSI layer registers */
40 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
56 /* SPI Master Registers */
66 /* Lane enable PPI and DSI register bits */
84 int ret = ctx->error; in tc358762_clear_error()
86 ctx->error = 0; in tc358762_clear_error()
92 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write() local
96 if (ctx->error) in tc358762_write()
106 ret = mipi_dsi_generic_write(dsi, data, sizeof(data)); in tc358762_write()
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H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
51 /* DSI PPI Layer Registers */
52 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
59 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
93 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
106 #define DSIERRCNT 0x0300 /* DSI Error Count */
173 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
32 /* PRCMU DSI reset registers */
73 d = host_to_mcde_dsi(mdsi->host); in mcde_dsi_irq()
75 dev_dbg(d->dev, "%s called\n", __func__); in mcde_dsi_irq()
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
81 dev_dbg(d->dev, "direct command write completed\n"); in mcde_dsi_irq()
84 dev_dbg(d->dev, "direct command TE received\n"); in mcde_dsi_irq()
87 dev_err(d->dev, "direct command ACK ERR received\n"); in mcde_dsi_irq()
89 dev_err(d->dev, "direct command read ERR received\n"); in mcde_dsi_irq()
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/linux/drivers/gpu/drm/sprd/
H A Dsprd_dsi.c1 // SPDX-License-Identifier: GPL-2.0
139 return (readl(ctx->base + offset) & mask) >> shift; in dsi_reg_rd()
148 ret = readl(ctx->base + offset); in dsi_reg_wr()
151 writel(ret, ctx->base + offset); in dsi_reg_wr()
158 u32 ret = readl(ctx->base + offset); in dsi_reg_up()
160 writel((ret & ~mask) | (val & mask), ctx->base + offset); in dsi_reg_up()
165 struct sprd_dsi *dsi = context; in regmap_tst_io_write() local
166 struct dsi_context *ctx = &dsi->ctx; in regmap_tst_io_write()
169 return -EINVAL; in regmap_tst_io_write()
171 drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val); in regmap_tst_io_write()
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
236 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
238 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
240 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
243 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
246 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); in mtk_dsi_phy_timconfig()
247 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
249 timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
250 timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000 + 1; in mtk_dsi_phy_timconfig()
251 timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
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/linux/arch/arm64/boot/dts/renesas/
H A Drzg2l-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
17 osc1: cec-clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12000000>;
23 hdmi-out {
24 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
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/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
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/linux/drivers/gpu/drm/panel/
H A Dpanel-raspberrypi-touchscreen.c2 * Copyright © 2016-2017 Broadcom
8 * Portions of this file (derived from panel-simple.c) are:
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
36 * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
40 * This driver controls the TC358762 and ATTINY88, presenting a DSI
47 #include <linux/media-bus-format.h>
58 #define RPI_DSI_DRIVER_NAME "rpi-ts-dsi"
83 /* DSI D-PHY Layer Registers */
94 /* DSI PPI Layer Registers */
118 /* DSI Protocol Layer Registers */
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