| /linux/drivers/clk/mmp/ |
| H A D | clk-frac.c | 37 do_div(rate, d->numerator * factor->masks->factor); in clk_factor_determine_rate()
56 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_recalc_rate() local
64 d.numerator = (val >> masks->num_shift) & masks->num_mask; in clk_factor_recalc_rate()
67 d.denominator = (val >> masks->den_shift) & masks->den_mask; in clk_factor_recalc_rate()
72 do_div(rate, d.numerator * factor->masks->factor); in clk_factor_recalc_rate()
82 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_set_rate() local
93 do_div(rate, d->numerator * factor->masks->factor); in clk_factor_set_rate()
104 val &= ~(masks->num_mask << masks->num_shift); in clk_factor_set_rate()
105 val |= (d->numerator & masks->num_mask) << masks->num_shift; in clk_factor_set_rate()
107 val &= ~(masks->den_mask << masks->den_shift); in clk_factor_set_rate()
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| /linux/sound/soc/codecs/ |
| H A D | tscs42xx.h | 124 /* Field Masks */
132 /* Register Masks */
147 /* Field Masks */
155 /* Register Masks */
170 /* Field Masks */
178 /* Register Masks */
195 /* Field Masks */
203 /* Register Masks */
220 /* Field Masks */
228 /* Register Masks */
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| H A D | cs42l56.h | 60 /* Device ID and Rev ID Masks */
66 /* Power bit masks */
78 /* serial port and clk masks */
96 /* Class H and misc ctl masks */
112 /* Playback Capture ctl masks */
130 /* Beep masks */
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| /linux/drivers/clk/spear/ |
| H A D | clk-aux-synth.c | 79 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; in clk_aux_recalc_rate()
80 if (eqn == aux->masks->eq1_mask) in clk_aux_recalc_rate()
84 num = (val >> aux->masks->xscale_sel_shift) & in clk_aux_recalc_rate()
85 aux->masks->xscale_sel_mask; in clk_aux_recalc_rate()
88 den *= (val >> aux->masks->yscale_sel_shift) & in clk_aux_recalc_rate()
89 aux->masks->yscale_sel_mask; in clk_aux_recalc_rate()
113 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); in clk_aux_set_rate()
114 val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << in clk_aux_set_rate()
115 aux->masks->eq_sel_shift; in clk_aux_set_rate()
116 val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); in clk_aux_set_rate()
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| /linux/lib/ |
| H A D | group_cpus.c | 47 cpumask_var_t *masks; in alloc_node_to_cpumask() local
50 masks = kcalloc(nr_node_ids, sizeof(cpumask_var_t), GFP_KERNEL); in alloc_node_to_cpumask()
51 if (!masks) in alloc_node_to_cpumask()
55 if (!zalloc_cpumask_var(&masks[node], GFP_KERNEL)) in alloc_node_to_cpumask()
59 return masks; in alloc_node_to_cpumask()
63 free_cpumask_var(masks[node]); in alloc_node_to_cpumask()
64 kfree(masks); in alloc_node_to_cpumask()
68 static void free_node_to_cpumask(cpumask_var_t *masks) in free_node_to_cpumask() argument
73 free_cpumask_var(masks[node]); in free_node_to_cpumask()
74 kfree(masks); in free_node_to_cpumask()
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| /linux/kernel/irq/ |
| H A D | affinity.c | 19 * irq_create_affinity_masks - Create affinity masks for multiqueue spreading
29 struct irq_affinity_desc *masks = NULL; in irq_create_affinity_masks() local
59 masks = kcalloc(nvecs, sizeof(*masks), GFP_KERNEL); in irq_create_affinity_masks()
60 if (!masks) in irq_create_affinity_masks()
65 cpumask_copy(&masks[curvec].mask, irq_default_affinity); in irq_create_affinity_masks()
76 kfree(masks); in irq_create_affinity_masks()
81 cpumask_copy(&masks[curvec + j].mask, &result[j]); in irq_create_affinity_masks()
94 cpumask_copy(&masks[curvec].mask, irq_default_affinity); in irq_create_affinity_masks()
98 masks[i].is_managed = 1; in irq_create_affinity_masks()
100 return masks; in irq_create_affinity_masks()
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| /linux/include/linux/ |
| H A D | intel_pmt_features.h | 8 /* Common masks */
24 /* Per Core Performance Telemetry (PCPT) specific masks */
31 /* Per Core Environmental Telemetry (PCET) specific masks */
44 /* Per RMID Performance Telemetry specific masks */
49 /* Accelerator Telemetry specific masks */
53 /* Uncore Telemetry specific masks */
59 /* Crash Log specific masks */
70 /* PeTe Log specific masks */
78 /* TPMI control specific masks */
82 /* Tracing specific masks */
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_cm.c | 119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
197 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in read_gamut_remap()
199 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in read_gamut_remap()
282 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
284 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
329 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
331 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
333 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
335 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
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| /linux/drivers/net/ethernet/ezchip/ |
| H A D | nps_enet.h | 35 /* Tx control register masks and shifts */
43 /* Rx control register masks and shifts */
53 /* Interrupt enable for data buffer events register masks and shifts */
59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
141 /* GE MAC, PCS reset control register masks and shifts */
147 /* Tx phase sync FIFO control register masks and shifts */
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| /linux/drivers/net/dsa/microchip/ |
| H A D | ksz8.c | 287 const u32 *masks; in ksz8_r_mib_cnt() local
294 masks = dev->info->masks; in ksz8_r_mib_cnt()
309 if (check & masks[MIB_COUNTER_VALID]) { in ksz8_r_mib_cnt()
311 if (check & masks[MIB_COUNTER_OVERFLOW]) in ksz8_r_mib_cnt()
323 const u32 *masks; in ksz8795_r_mib_pkt() local
330 masks = dev->info->masks; in ksz8795_r_mib_pkt()
347 if (check & masks[MIB_COUNTER_VALID]) { in ksz8795_r_mib_pkt()
356 if (check & masks[MIB_COUNTER_OVERFLOW]) { in ksz8795_r_mib_pkt()
362 if (check & masks[MIB_COUNTER_OVERFLOW]) in ksz8795_r_mib_pkt()
512 const u32 *masks; in ksz8_valid_dyn_entry() local
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| /linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| H A D | dcn30_dwb_cm.c | 53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
73 reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in dwb3_get_reg_field_ogam()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp_cm.c | 174 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
176 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
179 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
181 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
183 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
185 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
188 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
190 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
192 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
194 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; in dpp3_gamcor_reg_field()
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| /linux/arch/arm/mach-s3c/ |
| H A D | wakeup-mask.h | 27 * @masks: The list of masks to use.
28 * @nr_masks: The number of entries pointed to buy @masks.
31 * of interrupts and control bits in @masks. We do this at suspend time
36 const struct samsung_wakeup_mask *masks,
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| /linux/drivers/usb/gadget/udc/ |
| H A D | fsl_usb2_udc.h | 115 /* Frame Index Register Bit Masks */
117 /* USB CMD Register Bit Masks */
157 /* USB STS Register Bit Masks */
172 /* USB INTR Register Bit Masks */
183 /* Device Address bit masks */
187 /* endpoint list address bit masks */
190 /* PORTSCX Register Bit Masks */
254 /* otgsc Register Bit Masks */
281 /* USB MODE Register Bit Masks */
294 /* Endpoint Setup Status bit masks */
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| /linux/drivers/usb/misc/ |
| H A D | brcmstb-usb-pinmap.c | 154 res = of_property_read_u32_index(dn, "brcm,in-masks", index++, in parse_pins()
157 dev_err(dev, "Error getting 1st brcm,in-masks for %s\n", in parse_pins()
161 res = of_property_read_u32_index(dn, "brcm,in-masks", index++, in parse_pins()
164 dev_err(dev, "Error getting 2nd brcm,in-masks for %s\n", in parse_pins()
186 res = of_property_read_u32_index(dn, "brcm,out-masks", index++, in parse_pins()
189 dev_err(dev, "Error getting 1st brcm,out-masks for %s\n", in parse_pins()
193 res = of_property_read_u32_index(dn, "brcm,out-masks", index++, in parse_pins()
196 dev_err(dev, "Error getting 2nd brcm,out-masks for %s\n", in parse_pins()
200 res = of_property_read_u32_index(dn, "brcm,out-masks", index++, in parse_pins()
203 dev_err(dev, "Error getting 3rd brcm,out-masks for %s\n", in parse_pins()
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| /linux/drivers/media/pci/dt3155/ |
| H A D | dt3155.h | 69 /* CSR1 bit masks */
88 /* INT_CSR bit masks */
96 /* IIC_CSR1 bit masks */
99 /* IIC_CSR2 bit masks */
105 /* CSR2 bit masks */
115 /* CSR_EVEN/ODD bit masks */
120 /* CONFIG bit masks */
131 /* AD_CMD bit masks */
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| /linux/drivers/media/i2c/ |
| H A D | adv7393_regs.h | 92 /* Bit masks for Mode Select Register */
98 /* Bit masks for Mode Register 0 */
103 /* Bit masks for SD brightness/WSS */
107 /* Bit masks for soft reset register */
110 /* Bit masks for HD Mode Register 1 */
132 /* Bit masks for SD Mode Register 1 */
143 /* Bit masks for SD Mode Register 2 */
156 /* Bit masks for HD Mode Register 6 */
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| H A D | adv7343_regs.h | 84 /* Bit masks for Mode Select Register */
90 /* Bit masks for Mode Register 0 */
95 /* Bit masks for DAC output levels */
98 /* Bit masks for soft reset register */
101 /* Bit masks for HD Mode Register 1 */
123 /* Bit masks for SD Mode Register 1 */
134 /* Bit masks for SD Mode Register 2 */
147 /* Bit masks for HD Mode Register 6 */
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| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_flex_pipe.c | 143 /* 'dont_care' and 'nvr_mtch' masks cannot overlap */ in ice_gen_key_word()
225 * @upd: array of 8-bit masks that determine what key portion to update
226 * @dc: array of 8-bit masks that make up the don't care mask
227 * @nm: array of 8-bit masks that make up the never match mask
1172 /* Scan the enabled masks on this profile, for the specified idx */ in ice_prof_has_mask_idx()
1173 for (i = hw->blk[blk].masks.first; i < hw->blk[blk].masks.first + in ice_prof_has_mask_idx()
1174 hw->blk[blk].masks.count; i++) in ice_prof_has_mask_idx()
1176 if (hw->blk[blk].masks.masks[i].in_use && in ice_prof_has_mask_idx()
1177 hw->blk[blk].masks.masks[i].idx == idx) { in ice_prof_has_mask_idx()
1179 if (hw->blk[blk].masks.masks[i].mask == mask) in ice_prof_has_mask_idx()
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| /linux/security/landlock/ |
| H A D | ruleset.h | 227 * Returns: an access_masks result of the OR of all the domain's access masks.
237 .masks = domain->access_masks[layer_level],
243 return matches.masks;
273 landlock_get_applicable_domain(const struct landlock_ruleset * const domain,const struct access_masks masks) landlock_get_applicable_domain() argument
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| /linux/kernel/bpf/ |
| H A D | liveness.c | 113 /* Per frame, per instruction masks, frames allocated lazily. */
299 /* Accumulate may_read masks for @frame at @insn_idx */
303 struct per_frame_masks *masks; in mark_stack_read() local
306 masks = alloc_frame_masks(env, instance, frame, insn_idx); in mark_stack_read()
307 if (IS_ERR(masks)) in mark_stack_read()
308 return PTR_ERR(masks); in mark_stack_read()
309 new_may_read = masks->may_read | mask; in mark_stack_read()
310 if (new_may_read != masks->may_read && in mark_stack_read()
311 ((new_may_read | masks->live_before) != masks->live_before)) in mark_stack_read()
313 masks->may_read |= mask; in mark_stack_read()
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | brcm,usb-pinmap.yaml | 33 brcm,in-masks:
45 brcm,out-masks:
47 description: Array of enable, value, changed and clear masks, one
66 brcm,in-masks = <0x8000 0x40000 0x10000 0x80000>;
69 brcm,out-masks = <0x20000 0x800000 0x400000 0x200000>;
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| /linux/drivers/clk/uniphier/ |
| H A D | clk-uniphier-mux.c | 17 const unsigned int *masks; member
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent()
44 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent()
77 mux->masks = data->masks; in uniphier_clk_register_mux()
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | tdm-slot.txt | 20 tx and rx masks.
22 For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit
24 the masks.
26 The explicit masks are given as array of integers, where the first
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| /linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| H A D | dcn20_mpc.c | 165 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
167 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
223 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
225 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
251 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
253 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
255 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
257 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
259 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
261 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field()
[all …]
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