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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dti,omap-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
7 title: TI OMAP2+ and K3 Mailbox devices
13 The OMAP Mailbox hardware facilitates communication between different
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
46 Mailbox Controller Nodes
48 A Mailbox device node is used to represent a Mailbox IP instance/cluster
52 Mailbox User
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H A Domap-mailbox.txt1 OMAP2+ and K3 Mailbox
4 The OMAP mailbox hardware facilitates communication between different processors
5 using a queued mailbox interrupt mechanism. The IP block is external to the
10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
35 Mailbox Device Node:
37 A Mailbox device node is used to represent a Mailbox IP instance/cluster within
43 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
44 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
45 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
47 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
[all …]
H A Dhisilicon,hi6220-mailbox.txt1 Hisilicon Hi6220 Mailbox Driver
4 Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
9 Mailbox Device Node:
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
20 of cells required for the mailbox specifier. Must be 3.
22 phandle: Label name of mailbox controller
27 mailbox driver uses it to acknowledge interrupt
28 - interrupts: Contains the interrupt information for the mailbox
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
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H A Dmailbox.txt1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
4 assign appropriate mailbox channel to client drivers.
6 * Mailbox Controller
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
19 * Mailbox Client
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
27 users of these mailboxes for IPC, one for each mailbox. This shared
[all …]
H A Dapple,mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/apple,mailbox.yaml#
7 title: Apple Mailbox Controller
14 The Apple mailbox consists of two FIFOs used to exchange 64+32 bit
16 of this mailbox can be found on Apple SoCs.
31 - apple,t8103-asc-mailbox
32 - apple,t8112-asc-mailbox
33 - apple,t6000-asc-mailbox
34 - const: apple,asc-mailbox-v4
42 - apple,t8103-m3-mailbox
43 - apple,t8112-m3-mailbox
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H A Daltera-mailbox.txt1 Altera Mailbox Driver
5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
9 of cells required for the mailbox specifier. Should be 1.
16 mbox_tx: mailbox@100 {
17 compatible = "altr,mailbox-1.0";
24 mbox_rx: mailbox@200 {
25 compatible = "altr,mailbox-1.0";
32 Mailbox client
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H A Dmicrochip,mpfs-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
14 const: microchip,mpfs-mailbox
19 - description: mailbox control & data registers
20 - description: mailbox interrupt registers
23 - description: mailbox control registers
24 - description: mailbox interrupt registers
25 - description: mailbox data registers
46 mbox: mailbox@37020000 {
47 compatible = "microchip,mpfs-mailbox";
H A Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
6 There are total of 8 interrupts in this mailbox. Each used for an individual
7 door bell (or mailbox channel).
12 - reg: Contains the mailbox register address range.
15 the interrupt for mailbox channel 0 and interrupt 1 for
16 mailbox channel 1 and so likewise for the reminder.
18 - #mbox-cells: only one to specify the mailbox channel number.
22 Mailbox Node:
23 mailbox: mailbox@10540000 {
H A Dmediatek,gce-props.yaml4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
15 (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
16 mailbox framework. It is used to receive messages from mailbox consumers
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
20 registers is a mailbox consumer. The mailbox consumer can request a mailbox
22 that the GCE thread to configure its hardware. The mailbox provider can also
23 reserve a mailbox channel to configure GCE hardware register by the specific
24 GCE thread. This binding defines the common GCE properties for both mailbox
H A Dsti-mailbox.txt1 ST Microelectronics Mailbox Driver
3 Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages
10 - compatible : Should be "st,stih407-mailbox"
12 - mbox-name : Name of the mailbox
20 - interrupts : Contains the IRQ line for a Rx mailbox
24 mailbox0: mailbox@0 {
25 compatible = "st,stih407-mailbox";
38 - mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
47 compatible = "mailbox-test";
H A Dnvidia,tegra186-hsp.yaml4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
26 second cell is used to identify the mailbox that the client is going
32 mailbox to be used (based on the data size). If no flag is
33 specified then, 32-bit shared mailbox is used.
35 Defines the type of the mailbox to be used. This field should be
43 A bit mask of flags that further specify how the shared mailbox
46 Defines the direction of the mailbox. If set, the mailbox
48 cleared, the mailbox is the consumer of data sent by a
52 The index of the shared mailbox to use. The number of available
57 construct mailbox specifiers:
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H A Dst,sti-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/st,sti-mailbox.yaml#
7 title: STMicroelectronics Mailbox Driver for STi platform
10 Each ST Mailbox IP currently consists of 4 instances of 32 channels.
19 const: st,stih407-mailbox
26 description: name of the mailbox IP
29 description: the irq line for the RX mailbox
45 mailbox0: mailbox@8f00000 {
46 compatible = "st,stih407-mailbox";
H A Dxlnx,zynqmp-ipi-mailbox.txt1 Xilinx IPI Mailbox Controller
4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
35 - compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
40 - #address-cells: number of address cells of internal IPI mailbox nodes
41 - #size-cells: number of size cells of internal IPI mailbox nodes
43 Internal IPI mailbox node:
60 - xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
73 - mboxes: Standard property to specify a mailbox
74 (See ./mailbox.txt)
75 - mbox-names: List of identifier strings for each mailbox
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H A Dxlnx,zynqmp-ipi-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
41 - xlnx,zynqmp-ipi-mailbox
42 - xlnx,versal-ipi-mailbox
71 Remote Xilinx IPI agent ID of which the mailbox is connected to.
80 '^mailbox@[0-9a-f]+$':
81 description: Internal ipi mailbox node
88 - xlnx,zynqmp-ipi-dest-mailbox
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/freebsd/sys/dev/mlx4/mlx4_core/
H A Dmlx4_fw_qos.c87 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_PORT_PRIO2TC() local
93 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_PORT_PRIO2TC()
94 if (IS_ERR(mailbox)) in mlx4_SET_PORT_PRIO2TC()
95 return PTR_ERR(mailbox); in mlx4_SET_PORT_PRIO2TC()
97 context = mailbox->buf; in mlx4_SET_PORT_PRIO2TC()
103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, in mlx4_SET_PORT_PRIO2TC()
106 mlx4_free_cmd_mailbox(dev, mailbox); in mlx4_SET_PORT_PRIO2TC()
114 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_PORT_SCHEDULER() local
120 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_PORT_SCHEDULER()
121 if (IS_ERR(mailbox)) in mlx4_SET_PORT_SCHEDULER()
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H A Dmlx4_cq.c94 static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_SW2HW_CQ() argument
97 return mlx4_cmd(dev, mailbox->dma, cq_num, 0, in mlx4_SW2HW_CQ()
102 static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_MODIFY_CQ() argument
105 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ, in mlx4_MODIFY_CQ()
109 static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_HW2SW_CQ() argument
112 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, in mlx4_HW2SW_CQ()
113 cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ, in mlx4_HW2SW_CQ()
120 struct mlx4_cmd_mailbox *mailbox; in mlx4_cq_modify() local
124 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_cq_modify()
125 if (IS_ERR(mailbox)) in mlx4_cq_modify()
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H A Dmlx4_mcg.c54 struct mlx4_cmd_mailbox *mailbox, in mlx4_QP_FLOW_STEERING_ATTACH() argument
61 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0, in mlx4_QP_FLOW_STEERING_ATTACH()
83 struct mlx4_cmd_mailbox *mailbox) in mlx4_READ_ENTRY() argument
85 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG, in mlx4_READ_ENTRY()
90 struct mlx4_cmd_mailbox *mailbox) in mlx4_WRITE_ENTRY() argument
92 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG, in mlx4_WRITE_ENTRY()
97 struct mlx4_cmd_mailbox *mailbox) in mlx4_WRITE_PROMISC() argument
102 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1, in mlx4_WRITE_PROMISC()
107 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_GID_HASH() argument
113 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod, in mlx4_GID_HASH()
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H A Dmlx4_fw.c179 struct mlx4_cmd_mailbox *mailbox; in mlx4_MOD_STAT_CFG() local
188 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_MOD_STAT_CFG()
189 if (IS_ERR(mailbox)) in mlx4_MOD_STAT_CFG()
190 return PTR_ERR(mailbox); in mlx4_MOD_STAT_CFG()
191 inbox = mailbox->buf; in mlx4_MOD_STAT_CFG()
196 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, in mlx4_MOD_STAT_CFG()
199 mlx4_free_cmd_mailbox(dev, mailbox); in mlx4_MOD_STAT_CFG()
205 struct mlx4_cmd_mailbox *mailbox; in mlx4_QUERY_FUNC() local
220 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_QUERY_FUNC()
221 if (IS_ERR(mailbox)) in mlx4_QUERY_FUNC()
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H A Dmlx4_srq.c64 static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_SW2HW_SRQ() argument
67 return mlx4_cmd(dev, mailbox->dma, srq_num, 0, in mlx4_SW2HW_SRQ()
72 static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_HW2SW_SRQ() argument
75 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num, in mlx4_HW2SW_SRQ()
76 mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ, in mlx4_HW2SW_SRQ()
86 static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_QUERY_SRQ() argument
89 return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ, in mlx4_QUERY_SRQ()
166 struct mlx4_cmd_mailbox *mailbox; in mlx4_srq_alloc() local
181 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_srq_alloc()
182 if (IS_ERR(mailbox)) { in mlx4_srq_alloc()
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/freebsd/sys/dev/mthca/
H A Dmthca_cmd.c463 /* Invoke a command with an output mailbox */
607 struct mthca_mailbox *mailbox; in mthca_alloc_mailbox() local
609 mailbox = kmalloc(sizeof *mailbox, gfp_mask); in mthca_alloc_mailbox()
610 if (!mailbox) in mthca_alloc_mailbox()
613 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); in mthca_alloc_mailbox()
614 if (!mailbox->buf) { in mthca_alloc_mailbox()
615 kfree(mailbox); in mthca_alloc_mailbox()
619 return mailbox; in mthca_alloc_mailbox()
622 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) in mthca_free_mailbox() argument
624 if (!mailbox) in mthca_free_mailbox()
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H A Dmthca_mcg.c67 struct mthca_mailbox *mailbox; in find_mgm() local
72 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in find_mgm()
73 if (IS_ERR(mailbox)) in find_mgm()
75 mgid = mailbox->buf; in find_mgm()
79 err = mthca_MGID_HASH(dev, mailbox, hash); in find_mgm()
116 mthca_free_mailbox(dev, mailbox); in find_mgm()
123 struct mthca_mailbox *mailbox; in mthca_multicast_attach() local
131 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in mthca_multicast_attach()
132 if (IS_ERR(mailbox)) in mthca_multicast_attach()
133 return PTR_ERR(mailbox); in mthca_multicast_attach()
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/freebsd/sys/dev/ice/
H A Dice_vf_mbx.c46 * Send message to VF driver (0x0802) using mailbox
80 * Send message to PF driver using mailbox queue. By default, this
145 /* The mailbox overflow detection algorithm helps to check if there
148 * 1. The mailbox snapshot structure, ice_mbx_snapshot, is initialized during
151 * messages within the mailbox queue while looking for a malicious VF.
153 * 2. When the caller starts processing its mailbox queue in response to an
179 * in ice_mbx_snapshot for every new mailbox interrupt handled.
188 * ice_mbx_reset_snapshot - Initialize mailbox snapshot structure
189 * @snap: pointer to the mailbox snapshot
195 /* Clear mbx_buf in the mailbox snaphot structure and setting the in ice_mbx_reset_snapshot()
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_mbx.c42 * ixgbe_read_mbx - Reads a message from the mailbox
46 * @mbx_id: id of mailbox to read
56 /* limit read to size of mailbox */ in ixgbe_read_mbx()
59 "Invalid mailbox message size %u, changing to %u", in ixgbe_read_mbx()
71 * ixgbe_poll_mbx - Wait for message and read it from the mailbox
75 * @mbx_id: id of mailbox to read
90 /* limit read to size of mailbox */ in ixgbe_poll_mbx()
93 "Invalid mailbox message size %u, changing to %u", in ixgbe_poll_mbx()
107 * ixgbe_write_mbx - Write a message to the mailbox and wait for ACK
111 * @mbx_id: id of mailbox to write
[all …]
/freebsd/sys/dev/e1000/
H A De1000_mbx.c40 * @mbx_id: id of mailbox to read
55 * @mbx_id: id of mailbox to read
68 * e1000_read_mbx - Reads a message from the mailbox
72 * @mbx_id: id of mailbox to read
83 /* limit read to size of mailbox */ in e1000_read_mbx()
94 * e1000_write_mbx - Write a message to the mailbox
98 * @mbx_id: id of mailbox to write
121 * @mbx_id: id of mailbox to check
141 * @mbx_id: id of mailbox to check
161 * @mbx_id: id of mailbox to check
[all …]
/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dxlnx,zynqmp-power.txt13 "tx" - Mailbox corresponding to transmit path
14 "rx" - Mailbox corresponding to receive path
15 - mboxes : Standard property to specify a Mailbox. Each value of
17 mailbox controller device node and an args specifier
18 that will be the phandle to the intended sub-mailbox
20 Documentation/devicetree/bindings/mailbox/mailbox.txt
21 for more details about the generic mailbox controller
23 Documentation/devicetree/bindings/mailbox/ \
24 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
45 Example with IPI mailbox method:

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