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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/t
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H A Domap-mailbox.txt1 OMAP2+ and K3 Mailbox
4 The OMAP mailbox hardware facilitates communication between different processors
5 using a queued mailbox interrupt mechanism. The IP block is external to the
10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
25 routed to different processor sub-systems on DRA7xx as they are routed through
35 Mailbox Device Node:
37 A Mailbox device node is used to represent a Mailbox IP instance/cluster within
38 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
41 --------------------
42 - compatible: Should be one of the following,
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H A Dhisilicon,hi6220-mailbox.txt1 Hisilicon Hi6220 Mailbox Driver
4 Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
9 Mailbox Device Node:
13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
20 of cells required for the mailbox specifier. Must be 3.
22 phandle: Label name of mailbox controller
27 mailbox driver uses it to acknowledge interrupt
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H A Dmailbox.txt1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
4 assign appropriate mailbox channel to client drivers.
6 * Mailbox Controller
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
15 #mbox-cells = <1>;
19 * Mailbox Client
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
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H A Dapple,mailbox.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/apple,mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Mailbox Controller
10 - Hector Martin <marcan@marcan.st>
11 - Sven Peter <sven@svenpeter.dev>
14 The Apple mailbox consists of two FIFOs used to exchange 64+32 bit
15 messages between the main CPU and a co-processor. Multiple instances
16 of this mailbox can be found on Apple SoCs.
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H A Daltera-mailbox.txt1 Altera Mailbox Driver
5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
9 of cells required for the mailbox specifier. Should be 1.
12 - interrupts : interrupt number. The interrupt specifier format
16 mbox_tx: mailbox@100 {
17 compatible = "altr,mailbox-1.0";
19 interrupt-parent = < &gic_0 >;
21 #mbox-cells = <1>;
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H A Dmicrochip,mpfs-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
10 - Conor Dooley <conor.dooley@microchip.com>
14 const: microchip,mpfs-mailbox
18 - items:
19 - description: mailbox control & data registers
20 - description: mailbox interrupt registers
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H A Dmediatek,gce-props.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Houlong Wei <houlong.wei@mediatek.com>
13 The Global Command Engine (GCE) is an instruction based, multi-threaded,
14 single-core command dispatcher for MediaTek hardware. The Command Queue
15 (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
16 mailbox framework. It is used to receive messages from mailbox consumers
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
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H A Dsti-mailbox.txt1 ST Microelectronics Mailbox Driver
3 Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages
7 ----------
10 - compatible : Should be "st,stih407-mailbox"
11 - reg : Offset and length of the device's register set
12 - mbox-name : Name of the mailbox
13 - #mbox-cells: : Must be 2
20 - interrupts : Contains the IRQ line for a Rx mailbox
24 mailbox0: mailbox@0 {
25 compatible = "st,stih407-mailbox";
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H A Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
6 There are total of 8 interrupts in this mailbox. Each used for an individual
7 door bell (or mailbox channel).
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
16 mailbox channel 1 and so likewise for the reminder.
18 - #mbox-cells: only one to specify the mailbox channel number.
22 Mailbox Node:
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H A Dnvidia,tegra186-hsp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
26 second cell is used to identify the mailbox that the client is going
30 - bits 15..8:
32 mailbox to be used (based on the data size). If no flag is
33 specified then, 32-bit shared mailbox is used.
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H A Dxlnx,zynqmp-ipi-mailbox.txt1 Xilinx IPI Mailbox Controller
4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
8 +-------------------------------------+
10 +-------------------------------------+
11 +--------------------------------------------------+
15 +--------------------------+ |
18 +--------------------------------------------------+
19 +------------------------------------------+
20 | +----------------+ +----------------+ |
24 | +----------------+ +----------------+ |
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H A Dst,sti-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/st,sti-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics Mailbox Driver for STi platform
10 Each ST Mailbox IP currently consists of 4 instances of 32 channels.
15 - Patrice Chotard <patrice.chotard@foss.st.com>
19 const: st,stih407-mailbox
24 mbox-name:
26 description: name of the mailbox IP
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H A Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xln
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/freebsd/sys/dev/mlx4/mlx4_core/
H A Dmlx4_fw_qos.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
58 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
87 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_PORT_PRIO2TC() local
93 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_PORT_PRIO2TC()
94 if (IS_ERR(mailbox)) in mlx4_SET_PORT_PRIO2TC()
95 return PTR_ERR(mailbox); in mlx4_SET_PORT_PRIO2TC()
97 context = mailbox->buf; in mlx4_SET_PORT_PRIO2TC()
100 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1]; in mlx4_SET_PORT_PRIO2TC()
103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, in mlx4_SET_PORT_PRIO2TC()
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H A Dmlx4_cq.c18 * - Redistributions of source code must retain the above
22 * - Redistributions in binary form must reproduce the above
58 cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree, in mlx4_cq_completion()
59 cqn & (dev->caps.num_cqs - 1)); in mlx4_cq_completion()
65 ++cq->arm_sn; in mlx4_cq_completion()
67 cq->comp(cq); in mlx4_cq_completion()
72 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table; in mlx4_cq_event()
75 spin_lock(&cq_table->lock); in mlx4_cq_event()
77 cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1)); in mlx4_cq_event()
79 atomic_inc(&cq->refcount); in mlx4_cq_event()
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H A Dmlx4_mcg.c15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
45 return 1 << dev->oper_log_mgm_entry_size; in mlx4_get_mgm_entry_size()
50 return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2); in mlx4_get_qp_per_mgm()
54 struct mlx4_cmd_mailbox *mailbox, in mlx4_QP_FLOW_STEERING_ATTACH() argument
61 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0, in mlx4_QP_FLOW_STEERING_ATTACH()
83 struct mlx4_cmd_mailbox *mailbox) in mlx4_READ_ENTRY() argument
85 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG, in mlx4_READ_ENTRY()
90 struct mlx4_cmd_mailbox *mailbox) in mlx4_WRITE_ENTRY() argument
92 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG, in mlx4_WRITE_ENTRY()
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H A Dmlx4_fw.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
69 case 8: val = ((u64_p_t *)__p)->value; \
140 [7] = "FSM (MAC anti-spoofing) support", in dump_dev_cap_flags2()
143 [10] = "TCP/IP offloads/flow-steering for VXLAN support", in dump_dev_cap_flags2()
144 [11] = "MAD DEMUX (Secure-Host) support", in dump_dev_cap_flags2()
161 [28] = "RX-ALL support", in dump_dev_cap_flags2()
179 struct mlx4_cmd_mailbox *mailbox; in mlx4_MOD_STAT_CFG() local
188 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_MOD_STAT_CFG()
189 if (IS_ERR(mailbox)) in mlx4_MOD_STAT_CFG()
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H A Dmlx4_srq.c15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
45 struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; in mlx4_srq_event()
49 srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1)); in mlx4_srq_event()
52 atomic_inc(&srq->refcount); in mlx4_srq_event()
58 srq->event(srq, event_type); in mlx4_srq_event()
60 if (atomic_dec_and_test(&srq->refcount)) in mlx4_srq_event()
61 complete(&srq->free); in mlx4_srq_event()
64 static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_SW2HW_SRQ() argument
67 return mlx4_cmd(dev, mailbox->dma, srq_num, 0, in mlx4_SW2HW_SRQ()
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H A Dmlx4_mr.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
55 spin_lock(&buddy->lock); in mlx4_buddy_alloc()
57 for (o = order; o <= buddy->max_order; ++o) in mlx4_buddy_alloc()
58 if (buddy->num_free[o]) { in mlx4_buddy_alloc()
59 m = 1 << (buddy->max_order - o); in mlx4_buddy_alloc()
60 seg = find_first_bit(buddy->bits[o], m); in mlx4_buddy_alloc()
65 spin_unlock(&buddy->lock); in mlx4_buddy_alloc()
66 return -1; in mlx4_buddy_alloc()
69 clear_bit(seg, buddy->bits[o]); in mlx4_buddy_alloc()
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/freebsd/sys/dev/mthca/
H A Dmthca_cmd.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
154 * commands. So we can't use strict timeouts described in PRM -- we
193 return readl(dev->hcr + HCR_STATUS_OFFSET) & in go_bit()
205 void __iomem *ptr = dev->cmd.dbell_map; in mthca_cmd_post_dbell()
206 u16 *offs = dev->cmd.dbell_offsets; in mthca_cmd_post_dbell()
248 return -EAGAIN; in mthca_cmd_post_hcr()
256 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); in mthca_cmd_post_hcr()
257 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); in mthca_cmd_post_hcr()
258 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); in mthca_cmd_post_hcr()
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H A Dmthca_mcg.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
54 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
60 * If no AMGM exists for given gid, *index = -1, *prev = index of last
67 struct mthca_mailbox *mailbox; in find_mgm() local
68 struct mthca_mgm *mgm = mgm_mailbox->buf; in find_mgm()
72 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in find_mgm()
73 if (IS_ERR(mailbox)) in find_mgm()
74 return -ENOMEM; in find_mgm()
75 mgid = mailbox->buf; in find_mgm()
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/freebsd/sys/dev/ixgbe/
H A Dixgbe_mbx.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * ixgbe_read_mbx - Reads a message from the mailbox
46 * @mbx_id: id of mailbox to read
52 struct ixgbe_mbx_info *mbx = &hw->mbx; in ixgbe_read_mbx()
56 /* limit read to size of mailbox */ in ixgbe_read_mbx()
57 if (size > mbx->size) { in ixgbe_read_mbx()
59 "Invalid mailbox message size %u, changing to %u", in ixgbe_read_mbx()
60 size, mbx->size); in ixgbe_read_mbx()
61 size = mbx->size; in ixgbe_read_mbx()
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/freebsd/sys/dev/e1000/
H A De1000_mbx.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 * e1000_null_mbx_check_for_flag - No-op function, return 0
40 * @mbx_id: id of mailbox to read
51 * e1000_null_mbx_transact - No-op function, return 0
55 * @mbx_id: id of mailbox to read
68 * e1000_read_mbx - Reads a message from the mailbox
72 * @mbx_id: id of mailbox to read
78 struct e1000_mbx_info *mbx = &hw->mbx; in e1000_read_mbx()
79 s32 ret_val = -E1000_ERR_MBX; in e1000_read_mbx()
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/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dxlnx,zynqmp-power.txt1 --------------------------------------------------------------------
3 --------------------------------------------------------------------
4 The zynqmp-power node describes the power management configurations.
8 - compatible: Must contain: "xlnx,zynqmp-power"
9 - interrupts: Interrupt specifier
12 - mbox-names : Name given to channels seen in the 'mboxes' property.
13 "tx" - Mailbox corresponding to transmit path
14 "rx" - Mailbox corresponding to receive path
15 - mboxes : Standard property to specify a Mailbox. Each value of
17 mailbox controller device node and an args specifier
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