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/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
54 /* For NC-SI to register a fixed-link phy device */
68 /* Rx ring */
89 /* Scratch page to use when rx skb alloc fails */
100 struct clk *clk; member
103 struct clk *rclk;
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/linux/Documentation/devicetree/bindings/net/
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
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H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAC in Ingenic SoCs
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
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H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
23 transformer. This device interfaces directly to the MAC layer through the
34 nvmem-cells:
40 nvmem-cell-names:
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H A Dloongson,ls1b-gmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1B Gigabit Ethernet MAC Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1B Gigabit Ethernet MAC Controller is based on
14 Synopsys DesignWare MAC (version 3.50a).
17 - Dual 10/100/1000Mbps GMAC controllers
18 - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
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/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
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/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
27 Currently, this network device driver is for all STi embedded MAC/GMAC
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
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/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_define.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
27 #define MAC_INT_RX_DONE_L BIT(5) /* RX Low Priority Done */
28 #define MAC_INT_RX_DONE_H BIT(4) /* RX High Priority Done */
32 #define MAC_INT_RX_DES_ERR BIT(0) /* Rx Descriptor Error */
63 /* Wt mac ad0 */
77 /* W mac 15_0 bus */
80 /* W mac 47_16 bus */
154 /* MAC force mode */
171 #define RX_QUEUE0_DESC_NUM 16 /* # of descriptors in RX queue 0 */
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/linux/drivers/net/ethernet/broadcom/
H A Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 * hardware maximum rx/tx packet size including FCS, max mtu is
30 * actually 2047, but if we set max rx size register to 2047 we won't
199 /* mac irq, rx_dma irq, tx_dma irq */
204 /* hw view of rx & tx dma ring */
208 /* allocated size (in bytes) for rx & tx dma ring */
215 /* dma channel id for rx */
218 /* number of dma desc in rx ring */
221 /* cpu view of rx dma ring */
224 /* current number of armed descriptor given to hardware for rx */
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H A Dbcmsysport.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7xxx System Port Ethernet MAC driver
24 #include <linux/clk.h>
35 if (priv->is_lite && off >= RDMA_STATUS) in rdma_readl()
37 return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off); in rdma_readl()
42 if (priv->is_lite && off >= RDMA_STATUS) in rdma_writel()
44 writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off); in rdma_writel()
49 if (!priv->is_lite) { in tdma_control_bit()
59 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
60 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp133.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
14 reg-names = "m_can", "message_ram";
17 interrupt-names = "int0", "int1";
19 clock-names = "hclk", "cclk";
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
27 reg-names = "m_can", "message_ram";
30 interrupt-names = "int0", "int1";
32 clock-names = "hclk", "cclk";
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
16 #include <linux/clk.h>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
294 __raw_writel(val, eth->base + reg); in mtk_w32()
299 return __raw_readl(eth->base + reg); in mtk_r32()
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt7986a-bananapi-bpi-r3-mini.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Authors: Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
19 model = "Bananapi BPI-R3 Mini";
20 chassis-type = "embedded";
21 compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a";
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/linux/drivers/net/ethernet/marvell/
H A Dpxa168_eth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/clk.h>
16 #include <linux/dma-mapping.h>
38 #define DRIVER_NAME "pxa168-eth"
64 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
65 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
72 /* RX & TX descriptor command */
75 /* RX descriptor status */
158 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
173 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
8 #include <linux/clk.h>
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
39 * @soc_has_internal_phy: Does the MAC embed an internal PHY
40 * @support_mii: Does the MAC handle MII
41 * @support_rmii: Does the MAC handle RMII
42 * @support_rgmii: Does the MAC handle RGMII
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H A Dstmmac_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2011 STMicroelectronics Ltd
26 * dwmac1000_validate_mcast_bins - validates the number of Multicast filter bins
57 * dwmac1000_validate_ucast_entries - validate the Unicast address entries
88 * stmmac_axi_setup - parse DT parameters for programming the AXI register
91 * if required, from device-tree the AXI internal register can be tuned
99 np = of_parse_phandle(pdev->dev.of_node, "snps,axi-config", 0); in stmmac_axi_setup()
103 axi = devm_kzalloc(&pdev->dev, sizeof(*axi), GFP_KERNEL); in stmmac_axi_setup()
106 return ERR_PTR(-ENOMEM); in stmmac_axi_setup()
109 axi->axi_lpi_en = of_property_read_bool(np, "snps,lpi_en"); in stmmac_axi_setup()
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/linux/drivers/net/ethernet/atheros/
H A Dag71xx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Atheros AR71xx built-in ethernet mac driver
11 * David Bauer <mail@david-bauer.net>
14 * Hauke Mehrtens <hauke@hauke-m.de>
15 * Johann Neuhauser <johann@it-neuhauser.de>
17 * Jo-Philipp Wich <jo@mein.io>
39 #include <linux/clk.h>
43 /* For our NAPI weight bigger does *NOT* mean better - it means more
44 * D-cache misses and lots more wasted cycles than we'll ever
73 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qm.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
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/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/linux/drivers/net/ethernet/arc/
H A Demac_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
29 * arc_emac_tx_avail - Return the number of available slots in the tx ring.
36 return (priv->txbd_dirty + TX_BD_NUM - priv->txbd_curr - 1) % TX_BD_NUM; in arc_emac_tx_avail()
40 * arc_emac_adjust_link - Adjust the PHY link duplex.
49 struct phy_device *phy_dev = ndev->phydev; in arc_emac_adjust_link()
52 if (priv->link != phy_dev->link) { in arc_emac_adjust_link()
53 priv->link = phy_dev->link; in arc_emac_adjust_link()
57 if (priv->speed != phy_dev->speed) { in arc_emac_adjust_link()
58 priv->speed = phy_dev->speed; in arc_emac_adjust_link()
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H A Demac.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
12 #include <linux/dma-mapping.h>
15 #include <linux/clk.h>
32 #define RXRN_MASK (1 << 4) /* RX enable */
34 #define ENFL_MASK (1 << 10) /* Enable Full-duplex */
38 #define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
52 /* ARC EMAC register set combines entries for MAC and MDIO */
77 * struct arc_emac_bd - EMAC buffer descriptor (BD).
80 * @data: 32-bit byte addressable pointer to the packet data.
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/linux/Documentation/devicetree/bindings/firmware/
H A Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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/linux/drivers/net/ethernet/renesas/
H A Dravb.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
17 #include <linux/mdio-bitbang.h>
25 #define BE_RX_RING_SIZE 1024 /* RX ring size for Best Effort */
27 #define NC_RX_RING_SIZE 64 /* RX ring size for Network Control */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
46 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 /* AVB-DMAC registers */
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