| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | phy-mtk-ufs.txt | 1 MediaTek Universal Flash Storage (UFS) M-PHY binding
2 --------------------------------------------------------
4 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
5 Each UFS M-PHY node should have its own node.
7 To bind UFS M-PHY with UFS host controller, the controller node should
8 contain a phandle reference to UFS M-PHY node.
10 Required properties for UFS M-PHY nodes:
11 - compatible : Compatible list, contains the following controller:
12 "mediatek,mt8183-ufsphy" for ufs phy
14 - reg : Address and length of the UFS M-PHY register set.
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| H A D | mediatek,ufs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek Universal Flash Storage (UFS) M-PHY
11 - Stanley Chu <stanley.chu@mediatek.com>
12 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
16 Each UFS M-PHY node should have its own node.
17 To bind UFS M-PHY with UFS host controller, the controller node should
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| H A D | phy-mtk-tphy.txt | 1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and
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| H A D | phy-rockchip-inno-usb2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy with inno IP block
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
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| H A D | phy-mtk-xsphy.txt | 1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
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| H A D | rockchip,inno-usb2phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy wit
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| H A D | rockchip,rk3288-dp-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Analogix Display Port PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3288-dp-phy
19 clock-names:
20 const: 24m
22 "#phy-cells":
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| H A D | rockchip-dp-phy.txt | 1 Rockchip specific extensions to the Analogix Display Port PHY
2 ------------------------------------
5 - compatible : should be one of the following supported values:
6 - "rockchip.rk3288-dp-phy"
7 - clocks: from common clock binding: handle to dp clock.
9 - clock-names: from common clock binding:
10 Required elements: "24m"
11 - #phy-cells : from the generic PHY bindings, must be 0;
16 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
20 edp_phy: edp-phy {
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| /freebsd/tools/tools/net80211/wlantxtime/ |
| H A D | wlantxtime.c | 1 /*-
2 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
28 * IEEE 802.11 PHY-related support.
51 uint8_t phy; /* CCK/OFDM/TURBO */ member
72 exit(-1); \
84 exit(-1); in panic()
102 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
103 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
104 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
105 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
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| /freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
| H A D | cn9132-clearfog.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9132-sr-cex7.dtsi"
19 compatible = "solidrun,cn9132-clearfog",
20 "solidrun,cn9132-sr-cex7", "marvell,cn9130";
32 gpio-keys {
33 compatible = "gpio-keys";
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| H A D | cn9131-cf-solidwan.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
29 #include "armada-cp115.dtsi"
41 compatible = "solidrun,cn9131-solidwan",
42 "solidrun,cn9130-sr-som", "marvell,cn9130";
67 compatible = "gpio-leds";
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | nvidia,tegra234-mgbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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| H A D | sunplus,sp7021-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/sunplus,sp7021-emac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wells Lu <wellslutw@gmail.com>
14 Sunplus SP7021 dual 10M/100M Ethernet MAC controller.
19 const: sunplus,sp7021-emac
33 ethernet-ports:
36 description: Ethernet ports to PHY
39 "#address-cells":
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| H A D | qcom,qca807x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCA807x Ethernet PHY
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
14 Qualcomm QCA8072/5 Ethernet PHY is PHY package of 2 or 5
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
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| /freebsd/sys/dev/usb/net/ |
| H A D | if_udav.c | 3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
17 * 3. Neither the name of the author nor the names of any co-contributors
36 * DM9601(DAVICOM USB to Ethernet MAC Controller with Integrated 10/100 PHY)
38 * http://ptm2.cc.utu.fi/ftp/network/cards/DM9601/From_NET/DM9601-DS-P01-930914.pdf
174 /* Corega USB-TXC */
238 udav_csr_read(sc, UDAV_PAR, ue->ue_eaddr, ETHER_ADDR_LEN); in udav_attach_post()
246 if (uaa->usb_mode != USB_MODE_HOST) in udav_probe()
248 if (uaa->info.bConfigIndex != UDAV_CONFIG_INDEX) in udav_probe()
250 if (uaa->info.bIfaceIndex != UDAV_IFACE_INDEX) in udav_probe()
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| H A D | if_axe.c | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999, 2000-2003
18 * 4. Neither the name of the author nor the names of any co-contributors
52 * It uses an external PHY (reference designs use a RealTek chip),
53 * and has a 64-bit multicast hash filter. There is some information
57 * - You must set bit 7 in the RX control register, otherwise the
59 * - You must initialize all 3 IPG registers, or you won't be able
312 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); in axe_cmd()
318 axe_miibus_readreg(device_t dev, int phy, int reg) in axe_miibus_readreg() argument
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7915/ |
| H A D | debugfs.c | 1 // SPDX-License-Identifier: ISC
29 dev->ibf = !!val; in mt7915_implicit_txbf_set()
39 *val = dev->ibf; in mt7915_implicit_txbf_get()
52 struct mt7915_phy *phy = file->private_data; in mt7915_sys_recovery_set() local
53 struct mt7915_dev *dev = phy->dev; in mt7915_sys_recovery_set()
54 bool band = phy->mt76->band_idx; in mt7915_sys_recovery_set()
60 return -EINVAL; in mt7915_sys_recovery_set()
63 return -EFAULT; in mt7915_sys_recovery_set()
65 if (count && buf[count - 1] == '\n') in mt7915_sys_recovery_set()
66 buf[count - 1] = '\0'; in mt7915_sys_recovery_set()
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| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3588-friendlyelec-cm3588-nas.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/usb/pd.h>
15 #include "rk3588-friendlyelec-cm3588.dtsi"
19 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
21 adc_key_recovery: adc-key-recovery {
22 compatible = "adc-keys";
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| /freebsd/sys/contrib/device-tree/src/arm64/nvidia/ |
| H A D | tegra234-p3768-0000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "nvidia,p3768-0000";
11 stdout-path = "serial0:115200n8";
23 vcc-supply = <&vdd_1v8_sys>;
24 address-width = <8>;
27 read-only;
32 current-speed = <115200>;
37 assigned-clock
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| H A D | tegra234-p3768-0000+p3767.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
41 vcc-supply = <&vdd_1v8_sys>;
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| /freebsd/sys/dev/cxgb/ |
| H A D | cxgb_main.c | 2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
151 {PCI_VENDOR_ID_CHELSIO, 0x0036, 3, "S320E-CR"},
152 {PCI_VENDOR_ID_CHELSIO, 0x0037, 7, "N320E-G2"},
174 nitems(cxgb_identifiers) - 1);
226 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
238 "MSI-X, MSI, INTx selector");
241 * The driver uses an auto-queue algorithm by default.
242 * To disable it and force a single queue-set per port, use multiq = 0
246 "use min(ncpus/ports, 8) queue-sets per port");
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| /freebsd/sys/arm/allwinner/ |
| H A D | if_awg.c | 1 /*-
71 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
72 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
74 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
75 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
76 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
77 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
88 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1))
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| H A D | aw_usbphy.c | 1 /*-
27 * Allwinner USB PHY
46 #include <dev/phy/phy_usb.h>
133 { "allwinner,sun4i-a10-usb-phy", (uintptr_t)&a10_usbphy_conf },
134 { "allwinner,sun5i-a13-usb-phy", (uintptr_t)&a13_usbphy_conf },
135 { "allwinner,sun6i-a31-usb-phy", (uintptr_t)&a31_usbphy_conf },
136 { "allwinner,sun7i-a20-usb-phy", (uintptr_t)&a20_usbphy_conf },
137 { "allwinner,sun8i-h3-usb-phy", (uintptr_t)&h3_usbphy_conf },
138 { "allwinner,sun50i-a64-usb-phy", (uintptr_t)&a64_usbphy_conf },
139 { "allwinner,sun8i-a83t-usb-phy", (uintptr_t)&a83t_usbphy_conf },
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| /freebsd/sys/dev/bwn/ |
| H A D | if_bwn.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
544 sc->sc_dev = dev; in bwn_attach()
546 sc->sc_debug = bwn_debug; in bwn_attach()
553 sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices, in bwn_attach()
558 sc->sc_quirks |= bhnd_device_quirks(hostb, bridge_devices, in bwn_attach()
564 sc->sc_quirks |= BWN_QUIRK_NODMA; in bwn_attach()
567 sc->sc_cid = *bhnd_get_chipid(dev); in bwn_attach()
568 if ((error = bhnd_read_board_info(dev, &sc->sc_board_info))) { in bwn_attach()
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| /freebsd/sys/contrib/device-tree/src/riscv/microchip/ |
| H A D | mpfs-tysom-m.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2020-2022 - Aldec
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
9 /dts-v1/;
12 #include "mpfs-tyso
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