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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dmicrochip,sam9x75-lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip SAM9X75 LVDS Controller
10 - Dharma Balasubiramani <dharma.b@microchip.com>
13 The Low Voltage Differential Signaling Controller (LVDSC) manages data
14 format conversion from the LCD Controller internal DPI bus to OpenLDI
15 LVDS output signals. LVDSC functions include bit mapping, balanced mode
20 const: microchip,sam9x75-lvds
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H A Dlontium,lt9211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
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H A Dfsl,imx8qxp-pxl2dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 interfaces the pixel link 36-bit data output and the DSI controller’s
15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
16 used in LVDS mode, to remap the pixel color codings between those modules.
20 The CSR module, as a system controller, contains the PXL2DPI's configuration
25 const: fsl,imx8qxp-pxl2dpi
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H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
16 The CSR module, as a system controller, contains the LDB's configuration
23 LDB split mode to support a dual link LVDS display. The channel indexes
41 - fsl,imx8qm-ldb
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H A Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 asynchronous linkage between pixel sources(display controller or
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Timings Controller (TCON)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The TCON acts as a timing controller for RGB, LVDS and TV
18 "#clock-cells":
23 - const: allwinner,sun4i-a10-tcon
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H A Dst,stm32mp25-lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 LVDS Display Interface Transmitter
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
16 onto the LVDS PHY.
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H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
19 configuration of the controller takes place at logic configuration bitstream
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H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson Display Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic Meson Display controller is composed of several components
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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H A Drenesas,du.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
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/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/
H A Drockchip-lvds.txt1 Rockchip RK3288 LVDS interface
5 - compatible: matching the soc type, one of
6 - "rockchip,rk3288-lvds";
7 - "rockchip,px30-lvds";
9 - reg: physical base address of the controller and length
11 - clocks: must include clock specifiers corresponding to entries in the
12 clock-names property.
13 - clock-names: must contain "pclk_lvds"
15 - avdd1v0-supply: regulator phandle for 1.0V analog power
16 - avdd1v8-supply: regulator phandle for 1.8V analog power
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
10 - Liu Ying <victor.liu@nxp.com>
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
15 groups of four data lanes of LVDS data streams. A phase-locked
17 data streams over a fifth LVDS link. Every cycle of the transmit
19 through the two groups of LVDS data streams. Together with the
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/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
7 nodes describing each of the two LVDS encoder channels of the bridge.
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
15 interfaces as input for each LVDS channel.
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dmdp4.txt1 Qualcomm adreno/snapdragon MDP4 display controller
5 This is the bindings documentation for the MDP4 display controller found in
9 - compatible:
10 * "qcom,mdp4" - mdp4
11 - reg: Physical base address and length of the controller's registers.
12 - interrupts: The interrupt signal from the display controller.
13 - clocks: device clocks
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names: the following clocks are required.
22 - ports: contains the list of output ports from MDP. These connect to interfaces
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H A Dmdp5.txt1 Qualcomm adreno/snapdragon MDP5 display controller
6 controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
10 - compatible:
11 * "qcom,mdp5" - MDP5
12 - reg: Physical base address and length of the controller's registers.
13 - reg-names: The names of register regions. The following regions are required:
15 - interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
16 - clocks: device clocks. See ../clocks/clock-bindings.txt for details.
17 - clock-names: the following clocks are required.
18 - * "bus"
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H A Dmdp4.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Adreno/Snapdragon MDP4 display controller
10 MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
13 - Rob Clark <robdclark@gmail.com>
23 clock-names:
25 - const: core_clk
26 - const: iface_clk
27 - const: bus_clk
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dfsl,imx8qxp-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
13 As a system controller, the Freescale i.MX8qm/qxp Control and Status
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
23 pattern: "^syscon@[0-9a-f]+$"
27 - enum:
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dti,lmk04832.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments LMK04832 Clock Controller
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixe
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/freebsd/sys/contrib/device-tree/Bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-binding
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/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-nattis-2-natte-2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board
9 /dts-v1/;
10 #include "at91-linea.dtsi"
11 #include "at91-natte.dtsi"
14 model = "Axentia Linea-Nattis v2 Natte v2";
15 compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
18 gpio-keys {
19 compatible = "gpio-keys";
21 key-wakeup {
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/freebsd/sys/contrib/device-tree/Bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DPI and DP_INTF Controller
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
22 - mediatek,mt2701-dpi
23 - mediatek,mt7623-dpi
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H A Dmediatek,dpi.txt5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
9 - compatible: "mediatek,<chip>-dpi"
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "pixel", "engine", and "pll"
16 - port: Output port node with endpoint definitions as described in
18 to the input port of an attached HDMI or LVDS encoder chip.
21 - pinctrl-names: Contain "default" and "sleep".
[all …]

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