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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dst,stm32-ltdc.yaml4 $id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
15 const: st,stm32-ltdc
40 ltdc has one video port with up to 2 endpoints:
61 ltdc: display-controller@40016800 {
62 compatible = "st,stm32-ltdc";
H A Dst,stm32mp25-lvds.yaml15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
64 LVDS input port node, connected to the LTDC RGB output port.
H A Dst,stm32-dsi.yaml58 DSI input port node, connected to the ltdc rgb output port.
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp135.dtsi23 ltdc: display-controller@5a001000 { label
24 compatible = "st,stm32-ltdc";
H A Dstm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts78 &ltdc {
91 ltdc_pins: ltdc-0 {
H A Dstm32f429-disco.dts156 &ltdc {
194 /* Connect panel-ilitek-9341 to ltdc */
H A Dstm32mp157c-dk2.dts73 &ltdc {
H A Dstm32mp157a-icore-stm32mp1-ctouch2-of10.dts94 &ltdc {
H A Dstm32f746.dtsi601 ltdc: display-controller@40016800 { label
602 compatible = "st,stm32-ltdc";
605 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
H A Dstm32mp157a-icore-stm32mp1-edimm2.2.dts94 &ltdc {
H A Dstm32h743.dtsi353 ltdc: display-controller@50001000 { label
354 compatible = "st,stm32-ltdc";
357 resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
H A Dstm32f429.dtsi671 ltdc: display-controller@40016800 { label
672 compatible = "st,stm32-ltdc";
675 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
H A Dstm32mp157c-osd32mp1-red.dts133 &ltdc {
H A Dstm32f769-disco.dts177 &ltdc {
H A Dstm32f469-disco.dts171 &ltdc {
H A Dstm32f4-pinctrl.dtsi284 ltdc_pins_a: ltdc-0 {
318 ltdc_pins_b: ltdc-1 {
H A Dstm32mp157c-lxa-mc1.dts157 &ltdc {
H A Dstm32mp15-pinctrl.dtsi865 ltdc_pins_a: ltdc-0 {
902 ltdc_sleep_pins_a: ltdc-sleep-0 {
936 ltdc_pins_b: ltdc-1 {
973 ltdc_sleep_pins_b: ltdc-sleep-1 {
1007 ltdc_pins_c: ltdc-2 {
1043 ltdc_sleep_pins_c: ltdc-sleep-2 {
1071 ltdc_pins_d: ltdc-3 {
1113 ltdc_sleep_pins_d: ltdc-sleep-3 {
1147 ltdc_pins_e: ltdc-4 {
1190 ltdc_sleep_pins_e: ltdc-sleep-4 {
H A Dstm32429i-eval.dts240 &ltdc {
H A Dstm32mp15xx-dhcom-pdk2.dtsi213 &ltdc {
H A Dstm32mp157c-ev1.dts233 &ltdc {
H A Dstm32mp15xx-dhcor-avenger96.dtsi354 &ltdc {
H A Dstm32mp135f-dk.dts335 &ltdc {
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dst,stm32mp1-rcc.yaml38 For example on STM32MP1, for LTDC reset:
39 ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dstm32mp1-clks.h69 #define LTDC 56 macro

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