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Searched +full:ls1028a +full:- +full:reset (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dfsl,ls1028a-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas//soc/fsl/fsl,ls1028a-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape Reset Registers Module
10 - Frank Li
13 Reset Module includes chip reset, service processor control and Reset Control
18 pattern: "^syscon@[0-9a-f]+$"
22 - enum:
23 - fsl,ls1028a-reset
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "fsl,ls1028a";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
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H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
17 compatible = "kontron,sl28", "fsl,ls1028a";
33 compatible = "gpio-keys";
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H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/pci/
H A Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 This controller derives its clocks from the Reset Configuration Word (RCW)
16 which is used to describe the PLL settings at the time of chip-reset.
26 - enum:
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
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/linux/drivers/spi/
H A Dspi-nxp-fspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2019-2020 NXP
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
58 #include <linux/spi/spi-mem.h>
300 #define LUT_PAD(x) (fls(x) - 1)
306 * ---------------------------------------------------
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/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_ierb.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
4 * The Integrated Endpoint Register Block (IERB) is configured by pre-boot
7 * are read-only in the PF memory space.
9 * This driver fixes up the power-on reset values for the ENETC shared FIFO,
44 iowrite32(val, ierb->regs + offset); in enetc_ierb_write()
55 return -ENODEV; in enetc_ierb_register_pf()
58 return -EPROBE_DEFER; in enetc_ierb_register_pf()
62 * The power-on reset value (1800 bytes) is rounded up to the nearest in enetc_ierb_register_pf()
104 ierb = devm_kzalloc(&pdev->dev, sizeof(*ierb), GFP_KERNEL); in enetc_ierb_probe()
106 return -ENOMEM; in enetc_ierb_probe()
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/linux/drivers/pci/controller/dwc/
H A Dpci-layerscape-ep.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "pcie-designware.h"
35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl()
56 if (pcie->big_endian) in ls_pcie_pf_lut_readl()
57 return ioread32be(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
59 return ioread32(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
64 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_writel()
66 if (pcie->big_endian) in ls_pcie_pf_lut_writel()
67 iowrite32be(value, pci->dbi_base + offset); in ls_pcie_pf_lut_writel()
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H A Dpci-layerscape.c1 // SPDX-License-Identifier: GPL-2.0
26 #include "pcie-designware.h"
31 #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
46 #define PEXPME(idx) BIT(31 - (idx) * 4)
73 #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
77 struct dw_pcie *pci = pcie->pci; in ls_pcie_is_bridge()
80 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_is_bridge()
86 /* Clear multi-function bit */
89 struct dw_pcie *pci = pcie->pci; in ls_pcie_clear_multifunction()
91 iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_clear_multifunction()
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/linux/drivers/mmc/host/
H A Dsdhci-of-esdhc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/dma-mapping.h>
26 #include "sdhci-pltfm.h"
27 #include "sdhci-esdhc.h"
71 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
72 { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
73 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
74 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
75 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
76 { .compatible = "fsl,mpc8379-esdhc" },
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/linux/drivers/rtc/
H A Drtc-fsl-ftm-alarm.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2019-2020 NXP
47 if (dev->big_endian) in rtc_readl()
48 return ioread32be(dev->base + reg); in rtc_readl()
50 return ioread32(dev->base + reg); in rtc_readl()
55 if (dev->big_endian) in rtc_writel()
56 iowrite32be(val, dev->base + reg); in rtc_writel()
58 iowrite32(val, dev->base + reg); in rtc_writel()
87 *Fix errata A-007728 for flextimer in ftm_irq_acknowledge()
107 while ((FTM_SC_TOF & rtc_readl(rtc, FTM_SC)) && timeout--) in ftm_irq_acknowledge()
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/linux/drivers/tty/serial/
H A Dfsl_lpuart.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
14 #include <linux/dma-mapping.h>
30 /* All registers are 8-bit width */
119 /* 32-bit global registers only for i.MX7ULP/i.MX8x
120 * Used to reset all internal logic and registers, except the Global Register.
124 /* 32-bit register definition */
245 #define DRIVER_NAME "fsl-lpuart"
348 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
349 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
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/linux/drivers/crypto/caam/
H A Dctrl.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
45 /* INIT RNG in non-test mode */ in build_instantiation_desc()
95 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
97 * @ctrldev - pointer to device
98 * @status - descriptor status, after being run
100 * Return: - 0 if no error occurred
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/linux/drivers/net/dsa/ocelot/
H A Dfelix_vsc9959.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2018-2019 NXP
15 #include <linux/pcs-lynx.h>
663 /* Layer-3 Information */
669 /* Layer-4 Information */
900 /* soft-reset the switch core */ in vsc9959_reset()
906 dev_err(ocelot->dev, "timeout: switch core reset\n"); in vsc9959_reset()
916 dev_err(ocelot->dev, "timeout: switch sram init\n"); in vsc9959_reset()
928 * Bit 7-0: Value to be multiplied with unit
958 struct pci_dev *pdev = to_pci_dev(ocelot->dev); in vsc9959_mdio_bus_alloc()
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