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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,ls-extirq.txt3 Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
8 Supplemental Configuration Unit (SCFG).
11 - compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
12 "fsl,ls1043a-extirq": for LS1043A, LS1046A.
13 "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
14 - #interrupt-cells: Must be 2. The first element is the index of the
16 - #address-cells: Must be 0.
17 - interrupt-controller: Identifies the node as an interrupt controller
18 - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
19 the SCFG or the External Interrupt Control Register (IRQCR) in
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H A Dfsl,ls-extirq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,
20 - enum:
21 - fsl,ls1021a-extirq
22 - fsl,ls1043a-extirq
23 - fsl,ls1088a-extirq
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H A Dfsl,ls-scfg-msi.txt1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
14 - interrupts: an interrupt to the parent interrupt controller.
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H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
19 - Frank Li <Frank.Li@nxp.com>
24 - fsl,ls1012a-msi
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/freebsd/sys/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,layerscape-scfg.txt1 Freescale SCFG
3 SCFG is the supplemental configuration unit, that provides SoC specific
8 - compatible: Should contain a chip-specific compatible string,
9 Chip-specific strings are of the form "fsl,<chip>-scfg",
11 ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
13 - reg: should contain base address and length of SCFG memory-mapped registers
16 scfg: scfg@1570000 {
17 compatible = "fsl,ls1021a-scfg";
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/
H A Dfsl,layerscape-scfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-scfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 SCFG is the supplemental configuration unit, that provides SoC specific
20 - enum:
21 - fsl,ls1012a-scfg
22 - fsl,ls1021a-scfg
23 - fsl,ls1028a-scfg
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/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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H A Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 which is used to describe the PLL settings at the time of chip-reset.
26 - enum:
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
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