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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dcirrus,lochnagar.yaml87 codec-aif1-rxdat, codec-aif1-lrclk, codec-aif1-txdat,
88 codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk,
90 codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk,
91 dsp-aif1-rxdat, dsp-aif1-lrclk, dsp-aif1-txdat,
92 dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk,
93 dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk,
94 psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
96 gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk,
97 gf-aif4-rxdat, gf-aif4-lrclk, gf-aif4-txdat,
98 gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
[all …]
H A Dmarvell,armada-370-pinctrl.txt23 mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk)
66 mpp45 45 gpo, dev(ad6), audio(lrclk)
91 mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk)
H A Dmarvell,kirkwood-pinctrl.txt53 mpp41 41 gpio, audio(lrclk)
139 mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
188 mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
204 mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
253 mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
274 mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c65 #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
76 struct clk *lrclk; member
103 clk_prepare_enable(info->lrclk); in ep93xx_i2s_enable()
146 clk_disable_unprepare(info->lrclk); in ep93xx_i2s_disable()
257 /* Negative bit clock, lrclk low on left word */ in ep93xx_i2s_set_dai_fmt()
262 /* Negative bit clock, lrclk low on right word */ in ep93xx_i2s_set_dai_fmt()
268 /* Positive bit clock, lrclk low on left word */ in ep93xx_i2s_set_dai_fmt()
274 /* Positive bit clock, lrclk low on right word */ in ep93xx_i2s_set_dai_fmt()
318 * EP93xx I2S module can be setup so SCLK / LRCLK value can be in ep93xx_i2s_hw_params()
320 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK in ep93xx_i2s_hw_params()
[all …]
/linux/sound/soc/meson/
H A Daxg-tdm-formatter.c21 struct clk *lrclk; member
130 ret = clk_prepare_enable(formatter->lrclk); in axg_tdm_formatter_enable()
150 clk_disable_unprepare(formatter->lrclk); in axg_tdm_formatter_disable()
213 ret = clk_set_parent(formatter->lrclk_sel, ts->iface->lrclk); in axg_tdm_formatter_power_up()
303 formatter->lrclk = devm_clk_get(dev, "lrclk"); in axg_tdm_formatter_probe()
304 if (IS_ERR(formatter->lrclk)) in axg_tdm_formatter_probe()
305 return dev_err_probe(dev, PTR_ERR(formatter->lrclk), "failed to get lrclk\n"); in axg_tdm_formatter_probe()
413 ret = clk_prepare_enable(ts->iface->lrclk); in axg_tdm_stream_set_cont_clocks()
425 clk_disable_unprepare(ts->iface->lrclk); in axg_tdm_stream_set_cont_clocks()
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12.dtsi21 clock-names = "sclk", "lrclk", "mclk";
32 clock-names = "sclk", "lrclk", "mclk";
43 clock-names = "sclk", "lrclk", "mclk";
208 "lrclk", "lrclk_sel";
223 "lrclk", "lrclk_sel";
238 "lrclk", "lrclk_sel";
253 "lrclk", "lrclk_sel";
295 "lrclk", "lrclk_sel";
310 "lrclk", "lrclk_sel";
325 "lrclk", "lrclk_sel";
H A Dmeson-sm1.dtsi23 clock-names = "sclk", "lrclk", "mclk";
34 clock-names = "sclk", "lrclk", "mclk";
45 clock-names = "sclk", "lrclk", "mclk";
288 "lrclk", "lrclk_sel";
303 "lrclk", "lrclk_sel";
318 "lrclk", "lrclk_sel";
333 "lrclk", "lrclk_sel";
375 "lrclk", "lrclk_sel";
390 "lrclk", "lrclk_sel";
405 "lrclk", "lrclk_sel";
H A Dmeson-axg.dtsi31 clock-names = "sclk", "lrclk", "mclk";
42 clock-names = "sclk", "lrclk", "mclk";
53 clock-names = "sclk", "lrclk", "mclk";
1448 "lrclk", "lrclk_sel";
1462 "lrclk", "lrclk_sel";
1476 "lrclk", "lrclk_sel";
1490 "lrclk", "lrclk_sel";
1527 "lrclk", "lrclk_sel";
1541 "lrclk", "lrclk_sel";
1555 "lrclk", "lrclk_sel";
/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l33.txt54 LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
55 depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
57 cirrus,release-rate : The number of consecutive LRCLK periods before
58 allowing release condition tracking updates. The number of LRCLK periods
83 - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is
H A Dwlf,wm8960.yaml67 wlf,shared-lrclk:
75 enable DACLRC pin. If shared-lrclk is present, no need to enable DAC for
101 wlf,shared-lrclk;
H A Damlogic,axg-tdm-iface.yaml33 - const: lrclk
54 clock-names = "sclk", "lrclk", "mclk";
H A Damlogic,axg-tdm-formatters.yaml35 - const: lrclk
87 "lrclk", "lrclk_sel";
H A Dcirrus,ep9301-i2s.yaml41 - const: lrclk
77 clock-names = "mclk", "sclk", "lrclk";
H A Dmaxim,max98925.yaml52 32 BCLKS per LRCLK or 48 BCLKS per LRCLK.
H A Dfsl,sgtl5000.yaml56 lrclk-strength:
58 The LRCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
/linux/sound/soc/codecs/
H A Dwm8960.c141 int lrclk; member
195 if (abs(deemph_settings[i] - wm8960->lrclk) < in wm8960_set_deemph()
196 abs(deemph_settings[best] - wm8960->lrclk)) in wm8960_set_deemph()
625 * - lrclk = sysclk / dac_divs
631 * @dac_idx: dac_divs index for found lrclk
636 * >=0, in case we could derive bclk and lrclk from sysclk using
643 int sysclk, bclk, lrclk; in wm8960_configure_sysclk() local
651 lrclk = wm8960->lrclk; in wm8960_configure_sysclk()
659 if (sysclk != dac_divs[j] * lrclk) in wm8960_configure_sysclk()
682 * - sysclk = lrclk * dac_divs
[all …]
H A Darizona.c1447 int lrclk, bclk, mode, base; in arizona_set_fmt() local
1451 lrclk = 0; in arizona_set_fmt()
1487 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR; in arizona_set_fmt()
1494 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR; in arizona_set_fmt()
1507 lrclk |= ARIZONA_AIF1TX_LRCLK_INV; in arizona_set_fmt()
1513 lrclk |= ARIZONA_AIF1TX_LRCLK_INV; in arizona_set_fmt()
1525 ARIZONA_AIF1TX_LRCLK_MSTR, lrclk); in arizona_set_fmt()
1529 ARIZONA_AIF1RX_LRCLK_MSTR, lrclk); in arizona_set_fmt()
1755 int base, int bclk, int lrclk, int frame) in arizona_aif_cfg_changed() argument
1764 if (lrclk != (val & ARIZONA_AIF1RX_BCPF_MASK)) in arizona_aif_cfg_changed()
[all …]
H A Dmax98373-i2c.c172 /* BCLKs per LRCLK */
180 /* match BCLKs per LRCLK */ in max98373_get_bclk_sel()
192 /* BCLK/LRCLK ratio calculation */ in max98373_set_clock()
289 /* set DAI_SR to correct LRCLK frequency */ in max98373_dai_hw_params()
H A Dwm5100.c1285 int lrclk, bclk, mask, base; in wm5100_set_fmt() local
1289 lrclk = 0; in wm5100_set_fmt()
1309 lrclk |= WM5100_AIF1TX_LRCLK_MSTR; in wm5100_set_fmt()
1315 lrclk |= WM5100_AIF1TX_LRCLK_MSTR; in wm5100_set_fmt()
1329 lrclk |= WM5100_AIF1TX_LRCLK_INV; in wm5100_set_fmt()
1335 lrclk |= WM5100_AIF1TX_LRCLK_INV; in wm5100_set_fmt()
1344 WM5100_AIF1TX_LRCLK_INV, lrclk); in wm5100_set_fmt()
1346 WM5100_AIF1TX_LRCLK_INV, lrclk); in wm5100_set_fmt()
1405 int i, base, bclk, aif_rate, lrclk, wl, fl, sr; in wm5100_hw_params() local
1479 lrclk = bclk_rates[bclk] / params_rate(params); in wm5100_hw_params()
[all …]
H A Dwm2200.c1560 int lrclk, bclk, fmt_val; in wm2200_set_fmt() local
1562 lrclk = 0; in wm2200_set_fmt()
1582 lrclk |= WM2200_AIF1TX_LRCLK_MSTR; in wm2200_set_fmt()
1588 lrclk |= WM2200_AIF1TX_LRCLK_MSTR; in wm2200_set_fmt()
1602 lrclk |= WM2200_AIF1TX_LRCLK_INV; in wm2200_set_fmt()
1608 lrclk |= WM2200_AIF1TX_LRCLK_INV; in wm2200_set_fmt()
1618 lrclk); in wm2200_set_fmt()
1621 lrclk); in wm2200_set_fmt()
1693 int i, bclk, lrclk, wl, fl, sr_code; in wm2200_hw_params() local
1750 lrclk = bclk_rates[bclk] / params_rate(params); in wm2200_hw_params()
[all …]
H A Dmax98520.c122 /* BCLKs per LRCLK */
130 /* match BCLKs per LRCLK */ in max98520_get_bclk_sel()
143 /* BCLK/LRCLK ratio calculation */ in max98520_set_clock()
250 /* set DAI_SR to correct LRCLK frequency */ in max98520_dai_hw_params()
H A Dmax98090.c1499 if (!max98090->bclk || !max98090->lrclk) { in max98090_configure_bclk()
1510 /* Check for supported PCLK to LRCLK ratios */ in max98090_configure_bclk()
1513 (lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1515 "Found supported PCLK to LRCLK rates 0x%x\n", in max98090_configure_bclk()
1530 (user_lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1532 "Found user supported PCLK to LRCLK rates\n"); in max98090_configure_bclk()
1568 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) in max98090_configure_bclk()
1569 * (unsigned long long int)max98090->lrclk; in max98090_configure_bclk()
1941 max98090->lrclk = params_rate(params); in max98090_dai_hw_params()
1955 cdata->rate = max98090->lrclk; in max98090_dai_hw_params()
[all …]
/linux/sound/soc/fsl/
H A Dfsl_mqs.c109 int lrclk; in fsl_mqs_hw_params() local
112 lrclk = params_rate(params); in fsl_mqs_hw_params()
119 div = mclk_rate / (32 * lrclk * 2 * 8); in fsl_mqs_hw_params()
120 res = mclk_rate % (32 * lrclk * 2 * 8); in fsl_mqs_hw_params()
/linux/include/sound/
H A Dcs4271.h15 * The CS4271 requires its LRCLK and MCLK to be stable before its RESET
/linux/sound/soc/bcm/
H A Dcygnus-ssp.c543 bit_rate = aio->bit_per_frame * aio->lrclk; in cygnus_ssp_set_clocks()
568 dev_err(aio->cygaud->dev, "lrclk = %u, bits/frame = %u, mclk = %u\n", in cygnus_ssp_set_clocks()
569 aio->lrclk, aio->bit_per_frame, aio->mclk); in cygnus_ssp_set_clocks()
605 dev_dbg(aio->cygaud->dev, "bits per frame = %u, mclk = %u Hz, lrclk = %u Hz\n", in cygnus_ssp_set_clocks()
606 aio->bit_per_frame, aio->mclk, aio->lrclk); in cygnus_ssp_set_clocks()
694 aio->lrclk = rate; in cygnus_ssp_hw_params()
801 * 04 Yes LRCLK Polarity (1 = High for left, 0 = Low for left)

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