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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr4.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
7 title: LPDDR4 SDRAM compliant to JEDEC JESD209-4
18 - pattern: "^lpddr4-[0-9a-f]{2},[0-9a-f]{4}$"
19 - const: jedec,lpddr4
31 compatible = "lpddr4-ff,0100", "jedec,lpddr4";
H A Djedec,lpddr-channel.yaml23 - jedec,lpddr4-channel
85 const: jedec,lpddr4-channel
89 $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
128 compatible = "jedec,lpddr4-channel";
132 compatible = "lpddr4-05,0301", "jedec,lpddr4";
140 compatible = "lpddr4-05,0301", "jedec,lpddr4";
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt56 This parameter is for LPDDR4 only.
126 - rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
132 - rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
136 - rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
140 - rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
144 - rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
148 - rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
152 - rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
156 - rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml91 srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
225 When the DRAM type is LPDDR4, this parameter defines the ODT disable
233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
249 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
257 When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
265 When the DRAM type is LPDDR4, this parameter defines the PHY side clock
273 When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
281 When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
308 srpd_lite_idle nanoseconds. This parameter is for LPDDR4 onl
[all...]
H A Dnvidia,tegra186-mc.yaml15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt8103-pmgr.dtsi576 apple,always-on; /* LPDDR4 interface */
585 apple,always-on; /* LPDDR4 interface */
594 apple,always-on; /* LPDDR4 interface */
603 apple,always-on; /* LPDDR4 interface */
744 apple,always-on; /* LPDDR4 interface */
753 apple,always-on; /* LPDDR4 interface */
762 apple,always-on; /* LPDDR4 interface */
771 apple,always-on; /* LPDDR4 interface */
H A Dt8112-pmgr.dtsi530 apple,always-on; /* LPDDR4 interface */
539 apple,always-on; /* LPDDR4 interface */
548 apple,always-on; /* LPDDR4 interface */
557 apple,always-on; /* LPDDR4 interface */
566 apple,always-on; /* LPDDR4 interface */
575 apple,always-on; /* LPDDR4 interface */
584 apple,always-on; /* LPDDR4 interface */
593 apple,always-on; /* LPDDR4 interface */
/freebsd/sys/contrib/device-tree/Bindings/soc/renesas/
H A Drenesas,rzv2m-pwc.yaml13 - on/off signal generation for the LPDDR4 core power supply (LPVDD)
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drenesas,raa215300.yaml15 and LPDDR4 memory power requirements. The internally compensated regulators,
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-evkb.dts75 /* NVCC_DRAM for LPDDR4 */
H A Dimx93-tqma9352.dtsi113 /* V_DDRQ - 1.1 LPDDR4 or 0.6 LPDDR4X */
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm660-xiaomi-lavender.dts323 /* This gives power to the LPDDR4: never turn it off! */
H A Dsda660-inforce-ifc6560.dts312 /* This gives power to the LPDDR4: never turn it off! */
H A Dsdm630-sony-xperia-nile.dtsi541 /* This gives power to the LPDDR4: never turn it off! */
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dfsl.yaml1049 - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board