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Searched +full:lpddr2 +full:- +full:timings (Results 1 – 13 of 13) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/ddr/
H A Dlpddr2.txt1 * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
4 - compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
5 "jedec,lpddr2-s4"
7 "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
9 "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
11 "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
13 - density : <u32> representing density in Mb (Mega bits)
15 - io-width : <u32> representing bus width. Possible values are 8, 16, and 32
21 These values shall be obtained from the device data-sheet.
22 - tRRD-min-tck
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H A Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
4 - compatible : Should be "jedec,lpddr2-timings"
5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
11 data-sheet of the device for a given speed-bin. All these properties are
13 a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
14 - tRCD
15 - tWR
16 - tRAS-min
17 - tRRD
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H A Dlpddr3-timings.txt1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
3 The structures are based on LPDDR2 and extended where needed.
6 - compatible : Should be "jedec,lpddr3-timings"
7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
13 data-sheet of the device for a given speed-bin. All these properties are
15 - tRFC
16 - tRRD
17 - tRPab
18 - tRPpb
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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H A Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
4 - compatible : Should be "jedec,lpddr2-timings"
5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
11 data-sheet of the device for a given speed-bin. All these properties are
13 a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
14 - tRCD
15 - tWR
16 - tRAS-min
17 - tRRD
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H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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H A Dlpddr3-timings.txt1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
3 The structures are based on LPDDR2 and extended where needed.
6 - compatible : Should be "jedec,lpddr3-timings"
7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
13 data-sheet of the device for a given speed-bin. All these properties are
15 - tRFC
16 - tRRD
17 - tRPab
18 - tRPpb
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Delpida_ecb240abacn.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 elpida_ECB240ABACN: lpddr2 {
8 compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4";
10 io-width = <32>;
12 tRPab-min-tck = <3>;
13 tRCD-min-tck = <3>;
14 tWR-min-tck = <3>;
15 tRASmin-min-tck = <3>;
16 tRRD-min-tck = <2>;
17 tWTR-min-tck = <2>;
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
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H A Dtegra30-lg-p895.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
11 pinctrl-names = "default";
12 pinctrl-0 = <&state_default>;
15 /* GNSS UART-B pinmux */
16 uartb-cts-rxd {
22 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
24 uartb-rts-txd {
30 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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H A Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-binding
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
39 const: nvidia,tegra30-mc
47 clock-names:
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H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
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