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Searched full:lpddr (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/mtd/lpddr/
H A Dqinfo_probe.c20 static int lpddr_chip_setup(struct map_info *map, struct lpddr_private *lpddr);
24 struct lpddr_private *lpddr);
91 static int lpddr_pfow_present(struct map_info *map, struct lpddr_private *lpddr) in lpddr_pfow_present() argument
120 static int lpddr_chip_setup(struct map_info *map, struct lpddr_private *lpddr) in lpddr_chip_setup() argument
123 lpddr->qinfo = kzalloc_obj(struct qinfo_chip); in lpddr_chip_setup()
124 if (!lpddr->qinfo) in lpddr_chip_setup()
128 lpddr->ManufactId = CMDVAL(map_read(map, map->pfow_base + PFOW_MANUFACTURER_ID)); in lpddr_chip_setup()
130 lpddr->DevId = CMDVAL(map_read(map, map->pfow_base + PFOW_DEVICE_ID)); in lpddr_chip_setup()
132 lpddr->qinfo->DevSizeShift = lpddr_info_query(map, "DevSizeShift"); in lpddr_chip_setup()
133 lpddr->qinfo->TotalBlocksNum = lpddr_info_query(map, "TotalBlocksNum"); in lpddr_chip_setup()
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H A Dlpddr_cmds.c3 * LPDDR flash memory device operations. This module provides read, write,
4 * erase, lock/unlock support for LPDDR flash memories
37 struct lpddr_private *lpddr = map->fldrv_priv; in lpddr_cmdset() local
64 mtd->size = 1ULL << lpddr->qinfo->DevSizeShift; in lpddr_cmdset()
65 mtd->erasesize = 1 << lpddr->qinfo->UniformBlockSizeShift; in lpddr_cmdset()
66 mtd->writesize = 1 << lpddr->qinfo->BufSizeShift; in lpddr_cmdset()
68 shared = kmalloc_objs(struct flchip_shared, lpddr->numchips); in lpddr_cmdset()
74 chip = &lpddr->chips[0]; in lpddr_cmdset()
75 numchips = lpddr->numchips / lpddr->qinfo->HWPartsNum; in lpddr_cmdset()
79 for (j = 0; j < lpddr->qinfo->HWPartsNum; j++) { in lpddr_cmdset()
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H A DKconfig2 menu "LPDDR & LPDDR2 PCM memory drivers"
6 tristate "Support for LPDDR flash chips"
9 This option enables support of LPDDR (Low power double data rate)
17 Device Information for LPDDR chips is offered through the Overlay
H A DMakefile3 # linux/drivers/mtd/lpddr/Makefile
/linux/include/linux/mtd/
H A Dpfow.h3 * and service functions used by LPDDR chips
19 /* Identification info for LPDDR chip */
47 /* LPDDR memory device command codes */
H A Dqinfo.h13 /* lpddr_private describes lpddr flash chip in memory map
/linux/drivers/mtd/
H A DMakefile29 obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/
H A DKconfig217 source "drivers/mtd/lpddr/Kconfig"
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-sopine.dtsi114 regulator-name = "vdd-1v8-lpddr";
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916-pm8916.dtsi98 regulator-always-on; /* Needed for LPDDR RAM */
H A Dmsm8929-pm8916.dtsi76 regulator-always-on; /* Needed for LPDDR RAM */
/linux/include/soc/at91/
H A Dat91sam9_ddrsdr.h80 #define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */
/linux/drivers/acpi/pmic/
H A Dintel_pmic_bytcrc.c104 }, /* V18U -> V1P8U, LPDDR */
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h244 * we have 2 DPM and LPDDR, we will WM set A, B and
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-beacon-som.dtsi47 /* DDR controller is running LPDDR at 800MHz which requires 0.95V */
/linux/drivers/i2c/
H A Di2c-smbus.c429 case 0x1B: /* LPDDR */ in i2c_register_spd()
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi52 pp1200_lpddr: regulator-pp1200-lpddr {
/linux/drivers/memory/tegra/
H A Dtegra20-emc.c575 /* these registers are standard for all LPDDR JEDEC memory chips */ in emc_read_lpddr_sdram_info()
H A Dtegra30-emc.c1100 /* these registers are standard for all LPDDR JEDEC memory chips */ in emc_read_lpddr_sdram_info()