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Searched +full:lpc1850 +full:- +full:dac (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/iio/dac/
H A Dnxp,lpc1850-dac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/dac/nxp,lpc1850-dac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP LPC1850 DAC
10 - Jonathan Cameron <jic23@kernel.org>
13 Supports the DAC found on the LPC1850 SoC.
17 const: nxp,lpc1850-dac
28 vref-supply: true
34 - compatible
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H A Dlpc1850-dac.txt1 NXP LPC1850 DAC bindings
4 - compatible: Should be "nxp,lpc1850-dac"
5 - reg: Offset and length of the register set for the ADC device
6 - interrupts: The interrupt number for the ADC device
7 - clocks: The root clock of the ADC controller
8 - vref-supply: The regulator supply ADC reference voltage
9 - resets: phandle to reset controller and line specifier
12 dac: dac@400e1000 {
13 compatible = "nxp,lpc1850-dac";
17 vref-supply = <&reg_vdda>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc18xx.dtsi9 * Released under the terms of 3-clause BSD License
14 #include "../../armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
23 #address-cells = <1>;
24 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cell
453 dac: dac@400e1000 { global() label
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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dnxp,lpc1850-rgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nxp,lpc1850-rgu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP LPC1850 Reset Generation Unit (RGU)
10 - Frank Li <Frank.Li@nxp.com>
14 const: nxp,lpc1850-rgu
22 clock-names:
24 - const: delay
25 - const: reg
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H A Dnxp,lpc1850-rgu.txt1 NXP LPC1850 Reset Generation Unit (RGU)
8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
43 42 DAC
56 56 ARM Cortex-M0 application core (LPC4370 only)
59 60 ADCHS (12-bit ADC) (LPC4370 only)
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