| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | aspeed-lpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lp
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| H A D | aspeed-lpc.txt | 2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
7 primary use case of the Aspeed LPC controller is as a slave on the bus
11 The LPC controller is represented as a multi-function device to account for the
16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
17 physical properties of some LPC pins, configuration of serial IRQs, and
18 APB-to-LPC bridging amonst other functions.
20 * An LPC Host Interface Controller: Manages functions exposed to the host such
21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
28 Additionally the state of the LPC controller influences the pinmux
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| H A D | cros-ec.txt | 3 Google's ChromeOS EC is a Cortex-M device which talks to the AP and
6 The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the
8 its own driver which connects to the top level interface-agnostic EC driver.
9 Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
10 the top-level driver.
13 - compatible: "google,cros-ec-i2c"
14 - reg: I2C slave address
17 - compatible: "google,cros-ec-spi"
18 - reg: SPI chip select
21 - compatible: "google,cros-ec-rpmsg"
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| /freebsd/sys/contrib/device-tree/Bindings/ipmi/ |
| H A D | aspeed,ast2400-kcs-bmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kc
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| H A D | aspeed-kcs-bmc.txt | 5 used to perform in-band IPMI communication with their host.
9 - compatible : should be one of
10 "aspeed,ast2400-kcs-bmc"
11 "aspeed,ast2500-kcs-bmc"
12 - interrupts : interrupt generated by the controller
13 - kcs_chan : The LPC channel number in the controller
14 - kcs_addr : The host CPU IO map address
18 - compatible : should be one of
19 "aspeed,ast2400-kcs-bmc-v2"
20 "aspeed,ast2500-kcs-bmc-v2"
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| H A D | npcm7xx-kcs-bmc.txt | 5 used to perform in-band IPMI communication with their host.
8 - compatible : should be one of
9 "nuvoton,npcm750-kcs-bmc"
10 "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc"
11 - interrupts : interrupt generated by the controller
12 - kcs_chan : The KCS channel number in the controller
17 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
19 reg-io-width = <1>;
21 #address-cells = <1>;
22 #size-cells = <1>;
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| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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| /freebsd/sys/contrib/device-tree/Bindings/rtc/ |
| H A D | rtc-st-lpc.txt | 1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | st,stih407-lpc | 1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../rtc/rtc-st-lpc.txt for RTC options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
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| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | st_lpc_wdt.txt | 1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
24 - st,syscfg : Phandle to syscfg node used to enable watchdog and configure
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | lpc-eth.txt | 4 - compatible: Should be "nxp,lpc-eth"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain ethernet controller interrupt
9 - phy-mode: See ethernet.txt file in the same directory. If the property is
11 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
14 - mdio : specifies the mdio bus, used as a container for phy nodes according to
21 compatible = "nxp,lpc-eth";
23 interrupt-parent = <&mic>;
24 interrupts = <29 0>;
26 phy-mode = "rmii";
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| /freebsd/sys/contrib/device-tree/src/arm/aspeed/ |
| H A D | aspeed-g4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
35 #address-cells = <1>;
36 #size-cells = <0>;
39 compatible = "arm,arm926ej-s";
51 compatible = "simple-bus";
52 #address-cells = <1>;
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| H A D | aspeed-g6.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "aspeed,ast2600-smp";
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| H A D | aspeed-g5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
52 compatible = "simple-bus";
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| H A D | aspeed-bmc-amd-ethanolx.dts | 1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
26 compatible = "shared-dma-pool";
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| H A D | aspeed-bmc-tyan-s8036.dts | 1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "tyan,s8036-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
22 reserved-memory {
23 #address-cells = <1>;
24 #size-cells = <1>;
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| H A D | aspeed-bmc-asrock-e3c246d4i.dts | 1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/i2c/i2c.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 compatible = "asrock,e3c246d4i-bmc", "aspeed,ast2500";
18 stdout-path = &uart5;
27 compatible = "gpio-leds";
32 linux,default-trigger = "timer";
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| H A D | aspeed-bmc-asrock-romed8hm3.dts | 1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "asrock,romed8hm3-bmc", "aspeed,ast2500";
17 stdout-path = &uart5;
26 compatible = "gpio-leds";
30 linux,default-trigger = "timer";
33 system-fault {
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stih407-family.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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| /freebsd/usr.sbin/bhyve/ |
| H A D | bhyve.8 | 2 .\" SPDX-License-Identifier: BSD-2-Clause
102 I/O connectivity can be specified with command-line parameters.
113 .Pa edk2-bhyve
116 .Pa u-boot-bhyve-arm64
117 package provides a U-Boot image that can be used to boot the guest.
123 .Bl -tag -width 10n
164 Destroy the VM on guest initiated power-off.
206 Set configuration variables from a simple, key-value config file.
230 Print a list of supported LPC devices.
232 Allow devices behind the LPC PCI-ISA bridge to be configured.
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| H A D | bhyve_config.5 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
35 per-device settings.
69 For those variables the following case-insensitive values may be used to
72 .Bl -bullet -offset indent -compact
85 .Bl -bullet -offset indent -compact
103 .Bl -column "memory.guest_in_core" "integer" "Default"
140 This can cause problems if the guest uses the in-memory version, since certain
144 Destroy the VM on guest-initiated power-off.
149 If this is set to a non-zero value, a debug server
172 Use MSI-X interrupts for PCI VirtIO devices.
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| /freebsd/usr.sbin/bhyve/amd64/ |
| H A D | pci_lpc.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
87 * LPC device configuration is in the following form:
98 error = -1; in lpc_device_parse()
119 pci_parse_legacy_config(find_config_node("lpc"), in lpc_device_parse()
123 pci_parse_legacy_config(find_config_node("lpc"), str); in lpc_device_parse()
150 asprintf(&node_name, "lpc.%s.path", in lpc_device_parse()
159 asprintf(&node_name, "lpc.%s", pctestdev_getname()); in lpc_device_parse()
188 return (get_config_value("lpc.fwcfg")); in lpc_fwcfg()
196 assert(sc->irq >= 0); in lpc_uart_intr_assert()
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| /freebsd/sys/contrib/device-tree/Bindings/security/tpm/ |
| H A D | tpm_tis_mmio.txt | 5 this interface will be implemented over Intel's LPC bus.
12 - compatible: should contain a string below for the chip, followed by
13 "tcg,tpm-tis-mmio". Valid chip strings are:
15 - reg: The location of the MMIO registers, should be at least 0x5000 bytes
16 - interrupts: An optional interrupt indicating command completion.
21 compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio";
23 interrupt-parent = <&EIC0>;
24 interrupts = <1 2>;
|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | nuvoton,npcm845-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
13 The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
20 const: nuvoton,npcm845-pinctrl
25 '#address-cells':
28 '#size-cells':
44 gpio-controller: true
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| /freebsd/sys/contrib/device-tree/src/arm/nuvoton/ |
| H A D | nuvoton-common-npcm7xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-rese
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