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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rc6.c1 // SPDX-License-Identifier: MIT
24 * low-voltage mode when idle, using down to 0V while at this stage. This
30 * among each other with the latency required to enter and leave RC6 and
38 * require higher latency to switch to and wake up.
48 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
53 return rc6_to_gt(rc)->i915; in rc6_to_i915()
59 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable()
68 if (!intel_uc_uses_guc_rc(&gt->uc)) { in gen11_rc6_enable()
73 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen11_rc6_enable()
74 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen11_rc6_enable()
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/linux/drivers/nvme/host/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2011-2014, Intel Corporation.
9 #include <linux/blk-mq.h>
10 #include <linux/blk-integrity.h>
17 #include <linux/backing-dev.h>
29 #include <linux/nvme-auth.h>
72 "max power saving latency for new devices; use PM QOS to change per device");
91 "primary APST latency tolerance in us");
96 "secondary APST latency tolerance in us");
110 * nvme_wq - hosts nvme related works that are not reset or delete
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/linux/drivers/video/fbdev/riva/
H A Driva_hw.c3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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/linux/drivers/pci/pcie/
H A Daspm.c1 // SPDX-License-Identifier: GPL-2.0
49 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
65 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
73 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
84 struct pci_dev *parent = pdev->bus->self; in pci_save_aspm_l1ss_state()
96 if (!pdev->l1ss || !parent->l1ss) in pci_save_aspm_l1ss_state()
107 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
108 pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cap++); in pci_save_aspm_l1ss_state()
109 pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cap++); in pci_save_aspm_l1ss_state()
119 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
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/linux/drivers/gpu/drm/amd/include/
H A Dkgd_pp_interface.h88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
168 PP_SMC_POWER_PROFILE_UNKNOWN = -1,
238 * APU power is managed to system-level requirements through the PPT
248 * enum pp_power_limit_level - Used to query the power limits
256 PP_PWR_LIMIT_MIN = -1,
263 * enum pp_power_type - Used to specify the type of the requested power
276 XGMI_PLPD_NONE = -1,
284 PP_PM_POLICY_NONE = -1,
528 /* Driver attached timestamp (in ns) */
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/linux/drivers/net/ethernet/8390/
H A Dlib8390.c1 // SPDX-License-Identifier: GPL-1.0+
5 Written 1992-94 by Donald Becker.
16 This is the chip-specific code for many 8390-based ethernet adaptors.
17 This is not a complete driver, it must be combined with board-specific
23 you have found something that needs changing. -- PG
28 Paul Gortmaker : remove set_bit lock, other cleanups.
33 Paul Gortmaker : rewrite Rx overrun handling as per NS specs.
39 Paul Gortmaker : add kmod support for auto-loading of the 8390
79 /* These are the operational function interfaces to board-specific
88 "page" value uses the 8390's 256-byte pages.
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H A Daxnet_cs.c1 // SPDX-License-Identifier: GPL-1.0+
5 A PCMCIA ethernet driver for Asix AX88190-based cards
7 The Asix AX88190 is a NS8390-derived chipset with a few nasty
14 Copyright (C) 2001 David A. Hinds -- dahinds@users.sourceforge.net
52 #define AXNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
146 dev_dbg(&link->dev, "axnet_attach()\n"); in axnet_probe()
150 return -ENOMEM; in axnet_probe()
153 spin_lock_init(&ei_local->page_lock); in axnet_probe()
156 info->p_dev = link; in axnet_probe()
157 link->priv = dev; in axnet_probe()
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/linux/block/
H A Dblk-iolatency.c1 // SPDX-License-Identifier: GPL-2.0
3 * Block rq-qos base io controller
7 * - It's bio based, so the latency covers the whole block layer in addition to
9 * - We will throttle all IO that comes in here if we need to.
10 * - We use the mean latency over the 100ms window. This is because writes can
13 * - By default there's no throttling, we set the queue_depth to UINT_MAX so
17 * The hierarchy works like the cpu controller does, we track the latency at
19 * queue depth. This means that we only care about our latency targets at the
32 * an average latency of 5ms. If it does then we will throttle the "slow"
44 * number of IO's we're allowed to have in flight. This starts at (u64)-1 down
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H A Dbfq-iosched.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "blk-cgroup-rwstat.h"
29 * Soft real-time applications are extremely more latency sensitive
30 * than interactive ones. Over-raise the weight of the former to
38 * per-actuator data. The current value is hopefully a good upper
46 * struct bfq_service_tree - per ioprio_class service tree.
48 * Each service tree represents a B-WF2Q+ scheduler on its own. Each
50 * bfq_service_tree. All the fields are protected by the queue lock
71 * struct bfq_sched_data - multi-class scheduler.
81 * queue requests are served according to B-WF2Q+.
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/linux/drivers/usb/core/
H A Dhub.c1 // SPDX-License-Identifier: GPL-2.0
60 #define USB_TP_TRANSMISSION_DELAY 40 /* ns */
61 #define USB_TP_TRANSMISSION_DELAY_MAX 65535 /* ns */
62 #define USB_PING_RESPONSE_TIME 400 /* ns */
71 /* Protect struct usb_device->state and ->children members
72 * Note: Both are also protected by ->dev.sem, except that ->state can
80 /* synchronize hub-port add/remove and peering operations */
90 * 10 seconds to send reply for the initial 64-byte descriptor request.
92 /* define initial 64-byte descriptor request timeout in milliseconds */
96 "initial 64-byte descriptor request timeout in milliseconds "
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/linux/drivers/cpufreq/
H A Dpowernow-k8.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * (c) 2003-2006 Advanced Micro Devices, Inc.
9 u32 numps; /* number of p-states */
10 u32 batps; /* number of p-states supported on battery */
13 * vid/fid pairings, but are modified during the ->target() call
19 u32 plllock; /* pll lock time, units 1 us */
36 * handle hotplug events - so just point at cpufreq pol->cpus
53 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
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/linux/drivers/pmdomain/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/power/domain.c - Common code related to device power domains.
37 __routine = genpd->dev_ops.callback; \
48 void (*lock)(struct generic_pm_domain *genpd); member
56 mutex_lock(&genpd->mlock); in genpd_lock_mtx()
62 mutex_lock_nested(&genpd->mlock, depth); in genpd_lock_nested_mtx()
67 return mutex_lock_interruptible(&genpd->mlock); in genpd_lock_interruptible_mtx()
72 return mutex_unlock(&genpd->mlock); in genpd_unlock_mtx()
76 .lock = genpd_lock_mtx,
83 __acquires(&genpd->slock) in genpd_lock_spin()
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
20 { TIME_SYNC, { 4, -1 }, { 0, 0 }},
21 { ONE_PPS, { -1, 5 }, { 0, 11 }},
30 { TIME_SYNC, { 4, -1 }, { 11, 0 }},
31 { ONE_PPS, { -1, 5 }, { 0, 9 }},
40 { ONE_PPS, { -1, 5 }, { 0, 1 }},
53 { GNSS, { 1, -1 }, { 0, 0 }},
55 { UFL1, { -1, 0 }, { 0, 1 }},
57 { UFL2, { 3, -1 }, { 0, 0 }},
62 return !pf->adapter ? NULL : pf->adapter->ctrl_pf; in ice_get_ctrl_pf()
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/linux/fs/proc/
H A Dbase.c1 // SPDX-License-Identifier: GPL-2.0
9 * 1999, Al Viro. Rewritten. Now it covers the whole per-process part.
11 * we allocate and fill in-core inodes upon lookup. They don't even
18 * 17-Jan-2005
25 * Embedded Linux Lab - 10LE Instituto Nokia de Tecnologia - INdT
35 * 21-Feb-2005
36 * Embedded Linux Lab - 10LE Instituto Nokia de Tecnologia - INdT
40 * 10-Mar-2005
41 * 10LE Instituto Nokia de Tecnologia - INdT:
61 #include <linux/generic-radix-tree.h>
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/linux/drivers/md/
H A Ddm-ps-historical-service-time.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Keeps a time-weighted exponential moving average of the historical
20 * ns, and the weighting is pre-calculated.
25 #include "dm-path-selector.h"
32 #define DM_MSG_PREFIX "multipath historical-service-time"
48 spinlock_t lock; member
59 spinlock_t lock; member
70 * fixed_power - compute: x^n, in O(log n) time
94 result += 1UL << (frac_bits - 1); in fixed_power()
101 x += 1UL << (frac_bits - 1); in fixed_power()
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/linux/include/uapi/linux/
H A Dhdreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
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/linux/drivers/staging/media/ipu3/
H A Dipu3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 - 2018 Intel Corporation
16 #include "ipu3-css-fw.h"
17 #include "ipu3-dmamap.h"
18 #include "ipu3-mmu.h"
26 * pre-allocated buffer size for IMGU dummy buffers. Those
28 * re-allocation when streaming to lower streaming latency.
73 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe]; in imgu_dummybufs_cleanup()
77 &imgu_pipe->queues[i].dmap); in imgu_dummybufs_cleanup()
85 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe]; in imgu_dummybufs_preallocate()
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_ptp.c1 // SPDX-License-Identifier: GPL-2.0
27 struct igc_hw *hw = &adapter->hw; in igc_ptp_read()
34 ts->tv_sec = sec; in igc_ptp_read()
35 ts->tv_nsec = nsec; in igc_ptp_read()
41 struct igc_hw *hw = &adapter->hw; in igc_ptp_write_i225()
43 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
44 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
51 struct igc_hw *hw = &igc->hw; in igc_ptp_adjfine_i225()
58 scaled_ppm = -scaled_ppm; in igc_ptp_adjfine_i225()
80 spin_lock_irqsave(&igc->tmreg_lock, flags); in igc_ptp_adjtime_i225()
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/linux/kernel/sched/
H A Dfair.c1 // SPDX-License-Identifier: GPL-2.0
44 #include <linux/memory-tiers.h>
62 * The initial- and re-scaling of tunables is configurable
66 * SCHED_TUNABLESCALING_NONE - unscaled, always *1
67 * SCHED_TUNABLESCALING_LOG - scaled logarithmically, *1+ilog(ncpus)
68 * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus
75 * Minimal preemption granularity for CPU-bound tasks:
97 return -cpu; in arch_asym_cpu_priority()
118 * Amount of runtime to allocate from global (tg) to local (per-cfs_rq) pool
169 lw->weight += inc; in update_load_add()
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/linux/drivers/net/ethernet/freescale/
H A Dgianfar.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
67 #define DRV_NAME "gfar-enet"
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
106 /* Latency of interface clock in nanoseconds */
107 /* Interface clock latency , in this case, means the
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/linux/drivers/usb/host/
H A Dxhci.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/dma-mapping.h>
23 #include <linux/usb/xhci-sideband.h>
26 #include "xhci-trace.h"
27 #include "xhci-debugfs.h"
28 #include "xhci-dbgcap.h"
48 if (!td || !td->start_seg) in td_on_ring()
51 xhci_for_each_ring_seg(ring->first_seg, seg) { in td_on_ring()
52 if (seg == td->start_seg) in td_on_ring()
60 * xhci_handshake - spin reading hc until handshake completes or fails
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/linux/kernel/time/
H A Dhrtimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
4 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
5 * Copyright(C) 2006-2007 Timesys Corp., Thomas Gleixner
7 * High-resolution kernel timers
9 * In contrast to the low-resolution timeout API, aka timer wheel,
50 #include "tick-internal.h"
54 * cpu_base->active
57 #define HRTIMER_ACTIVE_HARD ((1U << MASK_SHIFT) - 1)
73 .lock = __RAW_SPIN_LOCK_UNLOCKED(hrtimer_bases.lock),
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/linux/drivers/platform/x86/intel/pmc/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <asm/intel-family.h>
62 return readl(pmc->regbase + reg_offset); in pmc_core_reg_read()
68 writel(val, pmc->regbase + reg_offset); in pmc_core_reg_write()
79 const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2; in pmc_core_adjust_slp_s0_step()
81 if (pmc->map == &adl_reg_map) in pmc_core_adjust_slp_s0_step()
84 return (u64)value * pmc->map->slp_s0_res_counter_step; in pmc_core_adjust_slp_s0_step()
89 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; in set_etr3()
90 const struct pmc_reg_map *map = pmc->map; in set_etr3()
93 if (!map->etr3_offset) in set_etr3()
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/linux/include/linux/
H A Dhyperv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
48 * gva: |-- 64k --|-- 64k --| ... |
59 * gva: |-- 64k --|-- 64k --| ... |-- 64k --|-- 64k --| ... |
69 * index: 0 1 2 ... 16 ... n-15 n-14 n-13 ... 2n-30
76 /* Single-page buffer */
83 /* Multiple-page buffer */
92 * Multiple-page buffer array; the pfn array is variable size:
123 * WS2012/Win8 and later versions of Hyper-V implement interrupt
125 * is set by the host on the host->guest ring buffer, and by the
126 * guest on the guest->host ring buffer.
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/linux/drivers/acpi/
H A Dcppc_acpi.c1 // SPDX-License-Identifier: GPL-2.0-only
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
20 * - Platform (such as BMC) is free to optimize request within requested bounds
23 * - Platform conveys its decision back to OS
59 * Lock to provide controlled access to the PCC channel.
69 * For non-performance critical usecases(init)
97 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_channel->shmem + \
101 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
102 (cpc)->cpc_entry.reg.space_id == \
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