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/freebsd/usr.bin/clang/llvm-symbolizer/
H A Dllvm-symbolizer.14 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
19 . nr rst2man-indent-level +1
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/freebsd/contrib/llvm-project/clang/lib/Basic/
H A DCuda.cpp3 #include "llvm/ADT/StringRef.h"
4 #include "llvm/ADT/Twine.h"
5 #include "llvm/Support/ErrorHandling.h"
6 #include "llvm/Support/VersionTuple.h"
13 llvm::VersionTuple TVersion;
18 llvm::VersionTuple(major, minor) \
31 CUDA_ENTRY(11, 0),
32 CUDA_ENTRY(11, 1),
33 CUDA_ENTRY(11, 2),
34 CUDA_ENTRY(11, 3),
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/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/PDB/
H A DPDBTypes.h1 //===- PDBTypes.h - Defines enums for various fields contained in PDB ----====//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 #include "llvm/ADT/APFloat.h"
13 #include "llvm/DebugInfo/CodeView/CodeView.h"
14 #include "llvm/DebugInfo/PDB/IPDBEnumChildren.h"
15 #include "llvm/DebugInfo/PDB/IPDBFrameData.h"
16 #include "llvm/DebugInfo/PDB/Native/RawTypes.h"
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DSpecifiers.h1 //===--- Specifiers.h - Declaration and Type Specifiers ---------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/Support/DataTypes.h"
20 #include "llvm/Support/ErrorHandling.h"
22 namespace llvm {
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H A Darm_fp16.td1 //===--- arm_fp16.td - ARM FP16 compiler interface ------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
16 // ARMv8.2-A FP16 intrinsics.
20 def VNEGSH : SInst<"vneg", "11", "Sh">;
24 def FSQRTSH : SInst<"vsqrt", "11", "Sh">;
28 def SCALAR_FRECPEH : IInst<"vrecpe", "11", "Sh">;
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H A DLangStandard.h1 //===--- LangStandard.h -----------------------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 #include "clang/Basic/LLVM.h"
13 #include "llvm/ADT/StringRef.h"
15 namespace llvm {
29 /// LLVM IR & CIR: we accept these so that we can run the optimizer on them,
30 /// and compile them to assembly or object code (or LLVM for CIR).
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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A Dppc64.cpp1 //===----- ppc64.cpp - Generic JITLink ppc64 edge kinds, utilities ----
17 namespace llvm::jitlink::ppc64 { global() namespace
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp1 //===-- RISCVAsmBackend.cpp - RISC-V Assembler Backend --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 #include "llvm/ADT/APInt.h"
12 #include "llvm/MC/MCAsmInfo.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCDirectives.h"
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td1 //===- XtensaInstrFormats.td - Xtensa Instruction Formats --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6 // See https://llvm.org/LICENSE.txt for license information.
7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9 //===----------------------------------------------------------------------===//
52 let Inst{23-20} = op2;
53 let Inst{19-16} = op1;
54 let Inst{15-12} = r;
55 let Inst{11-8} = s;
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterContext_x86.cpp1 //===-- RegisterContext_x86.cpp ---------------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 // Convert the 8-bit abridged FPU Tag Word (as found in FXSAVE) to the full
14 // 16-bit FPU Tag Word (as found in FSAVE, and used by gdb protocol). This
17 llvm::ArrayRef<MMSReg> st_regs) { in AbridgedToFullTagWord()
19 // Mapping to ST(i): i = FPU regno - TOP (Status Word, bits 11:13). in AbridgedToFullTagWord()
21 int st = 7 - ((sw >> 11) & 7); in AbridgedToFullTagWord()
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H A DARMUtils.h1 //===-- ARMUtils.h ----------------------------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 #include "llvm/ADT/bit.h"
15 #include "llvm/Support/MathExtras.h"
53 // A8.6.35 CMP (register) -- Encoding T3
62 // A8.6.35 CMP (register) -- Encoding A1
66 return DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); in DecodeImmShiftARM()
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H A DNetBSDSignals.cpp1 //===-- NetBSDSignals.cpp -------------------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
32 // clang-format off in Reset()
55 ADD_SIGCODE(SIGBUS, 10, BUS_ADRERR, 2, "non-existent physical address"); in Reset()
59 ADD_SIGCODE(SIGSEGV, 11, SEGV_MAPERR, 1, "address not mapped to object", in Reset()
61 ADD_SIGCODE(SIGSEGV, 11, SEGV_ACCERR, 2, "invalid permissions for mapped object", in Reset()
78 AddSignal(44, "SIGRTMIN+11", false, false, false, "real time signal 11"); in Reset()
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H A DLinuxSignals.cpp1 //===-- LinuxSignals.cpp --------------------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
41 // clang-format off in Reset()
79 AddSignal(11, "SIGSEGV", false, true, true, "segmentation violation"); in Reset()
80 …ADD_SIGCODE(SIGSEGV, 11, SEGV_MAPERR, 1, "address not mapped to object", SignalCodePrintOption::A… in Reset()
81 …ADD_SIGCODE(SIGSEGV, 11, SEGV_ACCERR, 2, "invalid permissions for mapped object", SignalCodePrint… in Reset()
82 …ADD_SIGCODE(SIGSEGV, 11, SEGV_BNDERR, 3, "failed address bounds checks", SignalCodePrintOption::B… in Reset()
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/ppc/
H A Dfixunstfdi.c1 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
2 // See https://llvm.org/LICENSE.txt for license information.
3 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // This file implements the PowerPC 128-bit double-double -> uint64_t conversion
15 (uint32_t)(hibits.x >> 32) - UINT32_C(0x3ff00000); in __fixunstfdi()
17 // If (1.0 - tiny) <= input < 0x1.0p64: in __fixunstfdi()
23 result <<= 11; // mantissa(hi) left aligned in the int64 field. in __fixunstfdi()
25 // If the tail is non-zero, we need to patch in the tail bits. in __fixunstfdi()
34 tailMantissa = (tailMantissa ^ negationMask) - negationMask; in __fixunstfdi()
36 // Now we have the mantissa of tail as a signed 2s-complement integer in __fixunstfdi()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.h1 //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions -------
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86ModRMFilters.h1 //===- X86ModRMFilters.h - Disassembler ModR/M filterss ---------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
22 namespace llvm {
26 /// ModRMFilter - Abstract base class for clases that recognize patterns in
32 /// Destructor - Override as necessary.
35 /// isDumb - Indicates whether this filter returns the same value for
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrFormats.td1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
23 def HasDSP : Predicate<"Subtarget->hasDSP()">,
25 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
27 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
64 // ADDU.QB sub-class format.
72 let Inst{25-21} = rs;
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H A DMipsMTInstrFormats.td1 //===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rt - destination register
15 //===----------------------------------------------------------------------===//
43 let Inst{31-26} = 0b010000; // COP0
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H A DMicroMipsDSPInstrFormats.td1 //===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
24 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
29 let Inst{31-26} = 0b000000;
30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
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/freebsd/contrib/llvm-project/llvm/include/llvm/Bitcode/
H A DLLVMBitCodes.h1 //===- LLVMBitCodes.h - Enum values for the LLVM bitcode format -*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This header defines Bitcode enum values for LLVM IR bitcode files.
15 //===----------------------------------------------------------------------===//
22 // changes without needing to fully or partially build LLVM itself.
23 #include "llvm/Bitstream/BitCodeEnums.h"
25 namespace llvm {
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "llvm/ADT/ArrayRef.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Support/Regex.h"
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/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DRandomNumberGenerator.h1 //==- llvm/Support/RandomNumberGenerator.h - RNG for diversity ---*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // cryptographically secure as it uses the C++11 <random> facilities.
13 //===----------------------------------------------------------------------===//
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/DataTypes.h" // Needed for uint64_t on Windows.
23 namespace llvm {
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparc.h1 //===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the entry points for global functions defined in the LLVM
10 // Sparc back-end.
12 //===----------------------------------------------------------------------===//
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetMachine.h"
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/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DSystemZ.cpp1 //===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
18 #include "llvm/ADT/StringSwitch.h"
49 return llvm::ArrayRef(GCCRegNames); in getGCCRegNames()
53 return llvm::ArrayRef(GCCAddlRegNames); in getGCCAddlRegNames()
66 case 'Q': // Address with base and unsigned 12-bit displacement in validateAsmConstraint()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V V extension instruction formats.
11 //===----------------------------------------------------------------------===//
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
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