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/linux/arch/mips/boot/dts/loongson/
H A Dloongson64v_4core_virtio.dts1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
5 /dts-v1/;
7 compatible = "loongson,loongson64v-4core-virtio";
8 #address-cells = <2>;
9 #size-cells = <2>;
11 cpuintc: interrupt-controller {
12 #address-cells = <0>;
13 #interrupt-cells = <1>;
14 interrupt-controller;
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H A Dloongson64g-package.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
6 #address-cells = <2>;
7 #size-cells = <2>;
9 cpuintc: interrupt-controller {
10 #address-cells = <0>;
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
16 package0: bus@1fe00000 {
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H A Dloongson64c-package.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
6 #address-cells = <2>;
7 #size-cells = <2>;
9 cpuintc: interrupt-controller {
10 #address-cells = <0>;
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
16 package0: bus@1fe00000 {
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H A Dloongson64c_8core_rs780e.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "rs780e-pch.dtsi"
9 compatible = "loongson,loongson64c-8core-rs780e";
13 htpic: interrupt-controller@1efdfb000080 {
14 compatible = "loongson,htpic-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
H A Dloongson64c_4core_rs780e.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "rs780e-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-rs780e";
13 htpic: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htpic-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
H A Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,liointc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips and
14 Loongson-2K series chips, as the primary package interrupt controller which
17 1.The Loongson-2K0500 is a single core CPU;
18 2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
19 need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
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H A Dloongson,htvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Vector Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips for
18 const: loongson,htvec-1.0
21 maxItems: 1
24 minItems: 1
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H A Dloongson,htpic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller is found in the Loongson-3 family of chips to transmit
21 const: loongson,htpic-1.0
24 maxItems: 1
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/linux/drivers/irqchip/
H A Dirq-loongson-liointc.c1 // SPDX-License-Identifier: GPL-2.0
25 #include "irq-loongson.h"
38 * LIOINTC_REG_INTC_POL register is only valid for Loongson-2K series, and
39 * Loongson-3 series behave as noops.
75 struct irq_chip_generic *gc = handler->priv->gc; in liointc_chained_handle_irq()
81 pending = readl(handler->priv->core_isr[core]); in liointc_chained_handle_irq()
85 if (handler->priv->has_lpc_irq_errata && in liointc_chained_handle_irq()
86 (handler->parent_int_map & gc->mask_cache & in liointc_chained_handle_irq()
96 generic_handle_domain_irq(gc->domain, bit); in liointc_chained_handle_irq()
108 writel(readl(gc->reg_base + offset) | mask, in liointc_set_bit()
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/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_TW.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
13 中的中斷控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片組的主中
16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
18 CPUINTC是一種CPU內部的每個核本地的中斷控制器，LIOINTC/EIOINTC/HTVECINTC是CPU內部的
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在這種模型裏面，IPI（Inter-Processor Interrupt）和CPU本地時鐘中斷直接發送到CPUINTC，
27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
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