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/linux/Documentation/devicetree/bindings/leds/
H A Dleds-bcm6328.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-bcm6328.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
17 as spi-gpio. See
21 exporting the 74x164 as spi-gpio prevents those LEDs to be hardware
25 should be controlled by a hardware signal instead of the MODE register value,
27 is usually 1:1 for hardware to LED signals, but through the activity/link
29 explained later in brcm,link-signal-sources). Even if a LED is hardware
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm63268-comtrend-vr-3032u.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 compatible = "comtrend,vr-3032u", "brcm,bcm63268";
8 model = "Comtrend VR-3032u";
17 stdout-path = &uart0;
23 brcm,serial-leds;
24 brcm,serial-dat-low;
25 brcm,serial-shift-inv;
29 brcm,hardware-controlled;
30 brcm,link-signal-sources = <0>;
[all …]
/linux/drivers/leds/
H A Dleds-bcm6328.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for BCM6328 memory-mapped LEDs, based on leds-syscon.c
59 * struct bcm6328_led - state container for bcm6328 based LEDs
98 * bits [31:0] -> LEDs 8-23
99 * bits [47:32] -> LEDs 0-7
100 * bits [63:48] -> unused
105 return pin + 16; /* LEDs 0-7 (bits 47:32) */ in bcm6328_pin2shift()
107 return pin - 8; /* LEDs 8-23 (bits 31:0) */ in bcm6328_pin2shift()
115 shift = bcm6328_pin2shift(led->pin); in bcm6328_led_mode()
117 mode = led->mem + BCM6328_REG_MODE_HI; in bcm6328_led_mode()
[all …]
/linux/Documentation/userspace-api/media/mediactl/
H A Dmedia-types.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _media-controller-types:
10 .. _media-entity-functions:
11 .. _MEDIA-ENT-F-UNKNOWN:
12 .. _MEDIA-ENT-F-V4L2-SUBDEV-UNKNOWN:
13 .. _MEDIA-ENT-F-IO-V4L:
14 .. _MEDIA-ENT-F-IO-VBI:
15 .. _MEDIA-ENT-F-IO-SWRADIO:
16 .. _MEDIA-ENT-F-IO-DTV:
17 .. _MEDIA-ENT-F-DTV-DEMOD:
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
/linux/drivers/comedi/drivers/
H A Dni_routes.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
33 * struct ni_route_set - Set of destinations with a common source.
34 * @dest: Destination of all sources in this route set.
35 * @n_src: Number of sources for this route set.
36 * @src: List of sources that all map to the same destination.
45 * struct ni_device_routes - List of all src->dest sets for a particular device.
46 * @device: Name of board/device (e.g. pxi-6733).
57 * struct ni_route_tables - Register values and valid routes for a device.
62 * Link to the valid src->dest routes and the register values used to assign
[all …]
/linux/Documentation/driver-api/
H A Dpps.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PPS - Pulse Per Second
22 --------
25 system several PPS sources.
28 provides a high precision signal each second so that an application
32 Carrier Detect pin) or to a parallel port (ACK-pin) or to a special
38 GPS receiver as PPS source, to obtain a wallclock-time with
39 sub-millisecond synchronisation to UTC.
43 ------------------
46 CPU GPIO-Pin as physical link to the signal, I encountered a deeper
[all …]
/linux/Documentation/sound/hd-audio/
H A Drealtek-pc-beep.rst20 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
24 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
43 into 21h (headphone jack on my machine). Mixed signal respects the mute
48 into 14h (internal speaker on my machine). Mixed signal **ignores** the mute
58 +--DIV--+--!DIV--+ {1Ah boost control}
60 +--(b == 0)--+--(b != 0)--+
70 +-----!h-----+-----S-----+
79 All Realtek HDA codecs have a vendor-defined widget with node ID 20h which
92 Specifically, it selects between two sources for the input pin widget with Node
93 ID (NID) 1Ah: the widget's signal can come either from an audio jack (on my
[all …]
/linux/drivers/media/i2c/
H A Dmax9286.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017-2019 Jacopo Mondi
6 * Copyright (C) 2017-2019 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
20 #include <linux/i2c-mux.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
[all …]
/linux/drivers/input/touchscreen/
H A Dwm9705.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm9705.c -- Codec driver for Wolfson WM9705 AC97 Codec.
56 * touchpanel plate and the ADC sampling the signal.
84 * Sources of glitch noise, such as signals driving an LCD display, may feed
86 * order to minimise this, a signal may be applied to the MASK pin to delay or
102 21, /* 1 AC97 Link frames */
123 * The delay is 3 AC97 link frames + the touchpanel settling delay
147 dev_dbg(wm->dev, in wm9705_phy_init()
150 dev_dbg(wm->dev, in wm9705_phy_init()
158 dev_dbg(wm->dev, "supplied delay out of range."); in wm9705_phy_init()
[all …]
H A Dwm9713.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm9713.c -- Codec touch driver for Wolfson WM9713 AC97 Codec.
69 * touchpanel plate and the ADC sampling the signal.
87 MODULE_PARM_DESC(five_wire, "Set to '1' to use 5-wire touchscreen.");
92 * Sources of glitch noise, such as signals driving an LCD display, may feed
94 * order to minimise this, a signal may be applied to the MASK pin to delay or
120 21, /* 1 AC97 Link frames */
141 * The delay is 3 AC97 link frames + the touchpanel settling delay
163 dev_info(wm->dev, "setting pen detect pull-up to %d Ohms\n", in wm9713_phy_init()
170 dev_info(wm->dev, "setting 5-wire touchscreen mode."); in wm9713_phy_init()
[all …]
H A Dwm9712.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm9712.c -- Codec driver for Wolfson WM9712 AC97 Codecs.
69 * touchpanel plate and the ADC sampling the signal.
87 MODULE_PARM_DESC(five_wire, "Set to '1' to use 5-wire touchscreen.");
92 * Sources of glitch noise, such as signals driving an LCD display, may feed
94 * order to minimise this, a signal may be applied to the MASK pin to delay or
120 21, /* 1 AC97 Link frames */
141 * The delay is 3 AC97 link frames + the touchpanel settling delay
160 dev_dbg(wm->dev, "setting pen detect pull-up to %d Ohms\n", in wm9712_phy_init()
167 dev_dbg(wm->dev, "setting 5-wire touchscreen mode.\n"); in wm9712_phy_init()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c50 #include "link.h"
74 * For eDP, after power-up/power/down,
84 hws->ctx
87 ctx->logger
89 struct dc_context *ctx = dc->ctx
92 hws->regs->reg
96 hws->shifts->field_name, hws->masks->field_name
104 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
107 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
110 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
[all …]
/linux/drivers/net/phy/
H A Ddp83822.c1 // SPDX-License-Identifier: GPL-2.0
149 struct net_device *ndev = phydev->attached_dev; in dp83822_config_wol()
153 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { in dp83822_config_wol()
154 mac = (const u8 *)ndev->dev_addr; in dp83822_config_wol()
157 return -EINVAL; in dp83822_config_wol()
171 if (wol->wolopts & WAKE_MAGIC) in dp83822_config_wol()
176 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83822_config_wol()
179 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83822_config_wol()
182 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83822_config_wol()
185 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83822_config_wol()
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
67 * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
83 * @pps_delay: propagation delay of the PPS output signal
85 * Characteristic information for the various TIME_REF sources possible in the
113 * Note that some values are not used for all link speeds, and the
115 * different link speeds, either the deskew marker for multi-lane link speeds
116 * or the Reed Solomon gearbox marker for RS-FEC.
136 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
200 * struct ice_cgu_pll_params_e82x - E82X CGU parameters
201 * @refclk_pre_div: Reference clock pre-divisor
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddcsr.txt21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
[all …]
/linux/include/sound/
H A Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
41 // This is used to define hardware bit-fields (sub-registers) by combining
44 // The non-concatenating (_NC) variant should be used directly only for
45 // sub-registers that do not follow the <register>_<field> naming pattern.
55 // Macros for manipulating values of bit-fields declared using the above macros.
59 // single sub-register at a time.
62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
[all …]
/linux/drivers/gpu/ipu-v3/
H A Dipu-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
31 return readl(ipu->cm_reg + offset); in ipu_cm_read()
36 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
41 return ipu->id; in ipu_get_num()
157 return -EINVAL; in ipu_degrees_to_rot_mode()
193 return -EINVAL; in ipu_rot_mode_to_degrees()
204 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
[all …]
/linux/sound/pci/ac97/
H A Dac97_patch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 err = snd_ctl_add(ac97->bus->card, snd_ac97_cnew(&controls[idx], ac97)); in patch_build_controls()
46 kctl = snd_ctl_find_id_mixer(ac97->bus->card, name); in reset_tlv()
47 if (kctl && kctl->tlv.p) in reset_tlv()
48 kctl->tlv.p = tlv; in reset_tlv()
57 mutex_lock(&ac97->page_mutex); in ac97_update_bits_page()
62 mutex_unlock(&ac97->page_mutex); /* unlock paging */ in ac97_update_bits_page()
67 * shared line-in/mic controls
80 ucontrol->value.enumerated.item[0] = ac97->indep_surround; in ac97_surround_jack_mode_get()
87 unsigned char indep = !!ucontrol->value.enumerated.item[0]; in ac97_surround_jack_mode_put()
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Ddiff-v4l.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _diff-v4l:
23 and below in :ref:`v4l-dev`.
25 The teletext devices (minor range 192-223) have been removed in V4L2 and
35 .. _v4l-dev:
37 .. flat-table:: V4L Device Types, Names and Numbers
38 :header-rows: 1
39 :stub-columns: 0
41 * - Device Type
42 - File Name
[all …]
/linux/drivers/iio/
H A Dindustrialio-backend.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -------------------------------------------------------
12 * ------------------ | ------------ ------------ ------- FPGA|
13 * | ADC |------------------------| | ADC CORE |---------| DMA CORE |------| RAM | |
14 * | (Frontend/IIO) | Serial Data (eg: LVDS) | |(backend) |---------| |------| | |
15 * | |------------------------| ------------ ------------ ------- |
16 * ------------------ -------------------------------------------------------
19 * - Backends should register themselves with devm_iio_backend_register()
20 * - Frontend devices should get backends with devm_iio_backend_get()
27 * the industrialio-backend.c is only left with the really generic stuff. Then,
[all …]
/linux/Documentation/networking/device_drivers/can/ctu/
H A Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
10 ------------------------
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
33 version of emulation support can be cloned from ctu-canfd branch of QEMU local
34 development `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
38 ---------------
59 it allows for device hot-plug.
[all …]
/linux/drivers/net/dsa/realtek/
H A Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 dc->ctx->logger
118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
[all …]
/linux/include/dt-bindings/clock/
H A Dtegra186-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
235 * @defgroup nafll_clks NAFLL clock sources
499 /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
501 /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
503 /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
818 * @brief GPC2CLK-div-2
842 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
898 /** @brief NAFLL clock source for M-CPU cluster */
900 /** @brief NAFLL clock source for B-CPU cluster */

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