| /linux/drivers/clk/renesas/ |
| H A D | rzv2h-cpg-lib.c | 20 * @limits: Pointer to the structure containing the limits for the PLL parameters
34 bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits, in rzv2h_cpg_get_pll_pars() argument
37 unsigned long input_fref = limits->input_fref ?: (24 * MEGA); in rzv2h_cpg_get_pll_pars()
38 u64 fout_min_millihz = mul_u32_u32(limits->fout.min, MILLI); in rzv2h_cpg_get_pll_pars()
39 u64 fout_max_millihz = mul_u32_u32(limits->fout.max, MILLI); in rzv2h_cpg_get_pll_pars()
49 for (p.p = limits->p.min; p.p <= limits->p.max; p.p++) { in rzv2h_cpg_get_pll_pars()
53 for (divider = 1 << limits->s.min, p.s = limits->s.min; in rzv2h_cpg_get_pll_pars()
54 p.s <= limits->s.max; p.s++, divider <<= 1) { in rzv2h_cpg_get_pll_pars()
55 for (p.m = limits->m.min; p.m <= limits->m.max; p.m++) { in rzv2h_cpg_get_pll_pars()
79 * limits->k.min <= pll_k <= limits->k.max in rzv2h_cpg_get_pll_pars()
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| /linux/drivers/net/ipa/ |
| H A D | ipa_resource.c | 35 /* We program at most 8 source or destination resource group limits */ in ipa_resource_limits_valid()
50 if (resource->limits[j].min || resource->limits[j].max) in ipa_resource_limits_valid()
63 if (resource->limits[j].min || resource->limits[j].max) in ipa_resource_limits_valid()
99 ylimits = group_count == 1 ? NULL : &resource->limits[1]; in ipa_resource_config_src()
101 &resource->limits[0], ylimits); in ipa_resource_config_src()
106 ylimits = group_count == 3 ? NULL : &resource->limits[3]; in ipa_resource_config_src()
108 &resource->limits[2], ylimits); in ipa_resource_config_src()
113 ylimits = group_count == 5 ? NULL : &resource->limits[5]; in ipa_resource_config_src()
115 &resource->limits[4], ylimits); in ipa_resource_config_src()
120 ylimits = group_count == 7 ? NULL : &resource->limits[7]; in ipa_resource_config_src()
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| /linux/drivers/infiniband/hw/mthca/ |
| H A D | mthca_main.c | 168 mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8; in mthca_dev_lim()
196 mdev->limits.num_ports = dev_lim->num_ports; in mthca_dev_lim()
197 mdev->limits.vl_cap = dev_lim->max_vl; in mthca_dev_lim()
198 mdev->limits.mtu_cap = dev_lim->max_mtu; in mthca_dev_lim()
199 mdev->limits.gid_table_len = dev_lim->max_gids; in mthca_dev_lim()
200 mdev->limits.pkey_table_len = dev_lim->max_pkeys; in mthca_dev_lim()
201 mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay; in mthca_dev_lim()
207 mdev->limits.max_sg = min_t(int, dev_lim->max_sg, in mthca_dev_lim()
214 mdev->limits.max_wqes = dev_lim->max_qp_sz; in mthca_dev_lim()
215 mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp; in mthca_dev_lim()
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| H A D | mthca_profile.c | 94 profile[MTHCA_RES_MTT].size = dev->limits.mtt_seg_size; in mthca_make_profile()
173 dev->limits.num_qps = profile[i].num; in mthca_make_profile()
178 dev->limits.num_eecs = profile[i].num; in mthca_make_profile()
183 dev->limits.num_srqs = profile[i].num; in mthca_make_profile()
188 dev->limits.num_cqs = profile[i].num; in mthca_make_profile()
199 dev->limits.num_eqs = profile[i].num; in mthca_make_profile()
212 dev->limits.num_mgms = profile[i].num >> 1; in mthca_make_profile()
213 dev->limits.num_amgms = profile[i].num >> 1; in mthca_make_profile()
220 dev->limits.num_mpts = profile[i].num; in mthca_make_profile()
226 dev->limits.num_mtt_segs = profile[i].num; in mthca_make_profile()
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| H A D | mthca_mr.c | 220 for (i = dev->limits.mtt_seg_size / 8; i < size; i <<= 1) in __mthca_alloc_mtt()
266 mtt->first_seg * dev->limits.mtt_seg_size + in __mthca_write_mtt()
319 mtts = dev->mr_table.tavor_fmr.mtt_base + mtt->first_seg * dev->limits.mtt_seg_size + in mthca_tavor_write_mtt_seg()
338 BUG_ON(s % dev->limits.mtt_seg_size); in mthca_arbel_write_mtt_seg()
341 s / dev->limits.mtt_seg_size, &dma_handle); in mthca_arbel_write_mtt_seg()
474 mr->mtt->first_seg * dev->limits.mtt_seg_size); in mthca_mr_alloc()
488 key & (dev->limits.num_mpts - 1)); in mthca_mr_alloc()
555 (dev->limits.num_mpts - 1)); in mthca_free_mr()
569 dev->limits.num_mpts, in mthca_init_mr_table()
570 ~0, dev->limits.reserved_mrws); in mthca_init_mr_table()
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| H A D | mthca_srq.c | 215 if (attr->max_wr > dev->limits.max_srq_wqes || in mthca_alloc_srq()
216 attr->max_sge > dev->limits.max_srq_sge) in mthca_alloc_srq()
232 if (!mthca_is_memfree(dev) && (ds > dev->limits.max_desc_sz)) in mthca_alloc_srq()
285 srq->srqn & (dev->limits.num_srqs - 1), in mthca_alloc_srq()
355 srq->srqn & (dev->limits.num_srqs - 1)); in mthca_free_srq()
437 srq = mthca_array_get(&dev->srq_table.srq, srqn & (dev->limits.num_srqs - 1)); in mthca_srq_event()
645 return dev->limits.max_sg; in mthca_max_srq_sge()
661 return min_t(int, dev->limits.max_sg, in mthca_max_srq_sge()
662 ((1 << (fls(dev->limits.max_desc_sz) - 1)) - in mthca_max_srq_sge()
677 dev->limits.num_srqs, in mthca_init_srq_table()
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| H A D | mthca_qp.c | 245 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1)); in mthca_qp_event()
317 param.port_width = dev->limits.port_width_cap; in init_port()
318 param.vl_cap = dev->limits.vl_cap; in init_port()
319 param.mtu_cap = dev->limits.mtu_cap; in init_port()
320 param.gid_cap = dev->limits.gid_table_len; in init_port()
321 param.pkey_cap = dev->limits.pkey_table_len; in init_port()
405 if (port_num == 0 || port_num > dev->limits.num_ports) in to_rdma_ah_attr()
423 (dev->limits.gid_table_len - 1), in to_rdma_ah_attr()
533 if (grh->sgid_index >= dev->limits.gid_table_len) { in mthca_path_set()
536 dev->limits.gid_table_len - 1); in mthca_path_set()
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| /linux/drivers/clk/ |
| H A D | clk-axi-clkgen.c | 65 struct axi_clkgen_limits limits; member
131 static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, in axi_clkgen_calc_params() argument
150 d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()
151 d_max = min(fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
154 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()
155 fvco_max_fract = limits->fvco_max << fract_shift; in axi_clkgen_calc_params()
349 const struct axi_clkgen_limits *limits = &axi_clkgen->limits; in axi_clkgen_set_rate() local
357 axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout); in axi_clkgen_set_rate()
398 const struct axi_clkgen_limits *limits = &axi_clkgen->limits; in axi_clkgen_determine_rate() local
402 axi_clkgen_calc_params(limits, req->best_parent_rate, req->rate, in axi_clkgen_determine_rate()
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| /linux/include/linux/ |
| H A D | blkdev.h | 361 * Flags automatically inherited when stacking limits.
412 /* atomic write limits */
537 struct queue_limits limits; member
615 * Protects queue limits and also sysfs attribute read_ahead_kb.
695 #define blk_queue_rot(q) ((q)->limits.features & BLK_FEAT_ROTATIONAL)
696 #define blk_queue_io_stat(q) ((q)->limits.features & BLK_FEAT_IO_STAT)
698 ((q)->limits.flags & BLK_FLAG_IOSTATS_PASSTHROUGH)
699 #define blk_queue_dax(q) ((q)->limits.features & BLK_FEAT_DAX)
700 #define blk_queue_pci_p2pdma(q) ((q)->limits.features & BLK_FEAT_PCI_P2PDMA)
716 ((q)->limits.features & BLK_FEAT_SKIP_TAGSET_QUIESCE)
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| /linux/security/apparmor/include/ |
| H A D | resource.h | 5 * This file contains AppArmor resource limits function definitions.
22 * @mask: which hard limits to set
23 * @limits: rlimit values that override task limits
26 * limits specified in @mask will be controlled by apparmor.
30 struct rlimit limits[RLIM_NLIMITS]; member
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| /linux/Documentation/admin-guide/sysctl/ |
| H A D | user.rst | 15 limits on the number of namespaces and other objects that have
16 per user per user namespace limits.
18 The primary purpose of these limits is to stop programs that
21 intention that the defaults of these limits are set high enough that
22 no program in normal operation should run into these limits.
31 limits in the user namespaces of those users.
34 user namespace does not allow a user to escape their current limits.
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| /linux/drivers/mfd/ |
| H A D | max14577.c | 42 * @limits: constraints for charger, matching the MBCICHWRC register
53 * - is always between <limits.min, limits.max>;
59 * is outside of given charger limits) and 'dst' is not set.
61 int maxim_charger_calc_reg_current(const struct maxim_charger_current *limits, in maxim_charger_calc_reg_current() argument
69 if (min_ua > limits->max || max_ua < limits->min) in maxim_charger_calc_reg_current()
72 if (max_ua < limits->high_start) { in maxim_charger_calc_reg_current()
81 /* max_ua is in range: <high_start, infinite>, cut it to limits.max */ in maxim_charger_calc_reg_current()
82 max_ua = min(limits->max, max_ua); in maxim_charger_calc_reg_current()
83 max_ua -= limits->high_start; in maxim_charger_calc_reg_current()
86 * - max_ua >= limits.high_start in maxim_charger_calc_reg_current()
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| /linux/Documentation/hwmon/ |
| H A D | lm77.rst | 27 The LM77 implements 3 limits: low (temp1_min), high (temp1_max) and
29 applies to all 3 limits. The relative difference is stored in a single
31 the limit and its hysteresis is always the same for all 3 limits.
44 hysteresis applies automatically to the low and high limits.
45 * The limits should be set before the hysteresis.
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| H A D | stpddc60.rst | 37 The vout under- and over-voltage limits are set in relation to the commanded
39 in 50mV steps. This means that the absolute values of the limits will change
41 writing to those limits since in the worst case the commanded output voltage
55 The following attributes are supported. Vin, iout, pout and temp limits
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| /linux/drivers/macintosh/ |
| H A D | therm_adt746x.c | 80 u8 limits[3]; member
216 " limits: %d,%d,%d;" in display_stats()
219 th->limits[0], th->limits[1], th->limits[2], in display_stats()
237 int var = th->temps[i] - th->limits[i]; in update_fans_speed()
314 th->limits[i] = default_limits_chip[i] + limit_adjust; in set_limit()
315 write_reg(th, LIMIT_REG[i], th->limits[i]); in set_limit()
317 /* set our limits to normal */ in set_limit()
318 th->limits[i] = default_limits_local[i] + limit_adjust; in set_limit()
357 printk(KERN_INFO "Adjusting limits by %d degrees\n", val); \
378 BUILD_SHOW_FUNC_INT(sensor1_limit, th->limits[1])
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-sg2044-pll.c | 73 const struct sg2044_pll_limit *limits; member
165 static int sg2042_pll_compute_postdiv(const struct sg2044_pll_limit *limits, in sg2042_pll_compute_postdiv() argument
177 for_each_pll_limit_range(div2, &limits[PLL_LIMIT_POSTDIV2]) { in sg2042_pll_compute_postdiv()
178 for_each_pll_limit_range(div1, &limits[PLL_LIMIT_POSTDIV1]) { in sg2042_pll_compute_postdiv()
207 static int sg2044_compute_pll_setting(const struct sg2044_pll_limit *limits, in sg2044_compute_pll_setting() argument
217 for_each_pll_limit_range(fbdiv, &limits[PLL_LIMIT_FBDIV]) { in sg2044_compute_pll_setting()
218 for_each_pll_limit_range(refdiv, &limits[PLL_LIMIT_REFDIV]) { in sg2044_compute_pll_setting()
221 if (!sg2044_clk_fit_limit(vco, &limits[PLL_LIMIT_FOUTVCO])) in sg2044_compute_pll_setting()
224 ret = sg2042_pll_compute_postdiv(limits, in sg2044_compute_pll_setting()
268 target = clamp(req->rate, pll->pll.limits[PLL_LIMIT_FOUT].min, in sg2044_pll_determine_rate()
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| /linux/drivers/platform/x86/ |
| H A D | intel_ips.c | 246 /* Per-SKU limits */
321 struct ips_mcp_limits *limits; member
400 * as low as the platform limits will allow (though we could go lower there
590 * mcp_exceeded - check whether we're outside our thermal & power limits
620 * cpu_exceeded - check whether a CPU core is outside its limits
636 if (avg > (ips->limits->core_temp_limit * 100)) in cpu_exceeded()
662 if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100)) in mch_exceeded()
672 * verify_limits - verify BIOS provided limits
675 * BIOS can optionally provide non-default limits for power and temp. Check
681 if (ips->mcp_power_limit < ips->limits->mcp_power_limit || in verify_limits()
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| H A D | asus-armoury.c | 862 * @limits: Pointer to the power_limits structure containing limit values
865 * It returns false if limits is NULL or if the corresponding limit value is zero.
869 static bool has_valid_limit(const char *name, const struct power_limits *limits) in has_valid_limit() argument
873 if (!limits) in has_valid_limit()
877 limit_value = limits->ppt_pl1_spl_max; in has_valid_limit()
879 limit_value = limits->ppt_pl2_sppt_max; in has_valid_limit()
881 limit_value = limits->ppt_pl3_fppt_max; in has_valid_limit()
883 limit_value = limits->ppt_apu_sppt_max; in has_valid_limit()
885 limit_value = limits->ppt_platform_sppt_max; in has_valid_limit()
887 limit_value = limits->nv_dynamic_boost_max; in has_valid_limit()
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| /linux/include/uapi/linux/ |
| H A D | dqblk_xfs.h | 37 #define Q_XGETQUOTA XQM_CMD(3) /* get disk limits and usage */
38 #define Q_XSETQLIM XQM_CMD(4) /* set disk limits */
43 #define Q_XGETNEXTQUOTA XQM_CMD(9) /* get disk limits and usage >= ID */
64 __s32 d_itimer; /* Zero if within inode limits. If
96 * automatically started and stopped. Superusers timer values set the limits
109 * below the soft limit). Superusers warning values set the warning limits
138 #define FS_QUOTA_UDQ_ENFD (1<<1) /* user quota limits enforcement */
140 #define FS_QUOTA_GDQ_ENFD (1<<3) /* group quota limits enforcement */
142 #define FS_QUOTA_PDQ_ENFD (1<<5) /* project quota limits enforcement */
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | selection-api-configuration.rst | 10 settings and hardware limits.
17 the source and the sink may have arbitrary upper and lower size limits.
50 The composing targets refer to a memory buffer. The limits of composing
61 to the bounding limits. Moreover, the driver can perform other
90 to be inserted into a video signal or graphical screen. The limits of
112 driver must adjust the area to fit to the bounding limits. Moreover, the
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| /linux/mm/ |
| H A D | shmem_quota.c | 8 * can lose valuable information, user provided limits, because there is
39 * before the soft limits are treated as hard limits (usually resulting
63 * set limits
161 * Load dquot with limits from existing entry, or create the new entry if
214 /* Load the stored limits from the tree */ in shmem_acquire_dquot()
261 * Store limits from dquot in the tree unless it's fake. If it is fake
303 /* Store the limits in the tree */ in shmem_release_dquot()
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| /linux/block/ |
| H A D | blk.h | 22 * controlled by the block device driver, usually based on hardware limits.
234 return min(q->limits.max_discard_sectors, in blk_queue_get_max_sectors()
238 return min(q->limits.max_secure_erase_sectors, in blk_queue_get_max_sectors()
242 return q->limits.max_write_zeroes_sectors; in blk_queue_get_max_sectors()
245 return q->limits.atomic_write_max_sectors; in blk_queue_get_max_sectors()
247 return q->limits.max_sectors; in blk_queue_get_max_sectors()
281 return bvec_gap_to_prev(&req->q->limits, in integrity_req_gap_back_merge()
292 return bvec_gap_to_prev(&req->q->limits, in integrity_req_gap_front_merge()
349 * Plug flush limits
417 * __bio_split_to_limits - split a bio to fit the queue limits
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | legacy_dpm.c | 384 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits = in amdgpu_parse_extended_power_table() local
394 1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record))); in amdgpu_parse_extended_power_table()
398 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
405 limits->numEntries; in amdgpu_parse_extended_power_table()
406 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
408 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
445 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits = in amdgpu_parse_extended_power_table() local
451 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
458 limits->numEntries; in amdgpu_parse_extended_power_table()
459 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ |
| H A D | ipsec_offload.c | 393 if (!sa_entry->limits.soft_limit_hit && in mlx5e_ipsec_handle_limits()
394 sa_entry->limits.round == attrs->lft.numb_rounds_soft) { in mlx5e_ipsec_handle_limits()
395 sa_entry->limits.soft_limit_hit = true; in mlx5e_ipsec_handle_limits()
399 if (sa_entry->limits.round == attrs->lft.numb_rounds_hard) in mlx5e_ipsec_handle_limits()
416 sa_entry->limits.fix_limit = true; in mlx5e_ipsec_handle_limits()
420 sa_entry->limits.fix_limit = true; in mlx5e_ipsec_handle_limits()
424 if (sa_entry->limits.round == attrs->lft.numb_rounds_hard) { in mlx5e_ipsec_handle_limits()
431 sa_entry->limits.round++; in mlx5e_ipsec_handle_limits()
432 if (sa_entry->limits.round == attrs->lft.numb_rounds_soft) in mlx5e_ipsec_handle_limits()
435 if (sa_entry->limits.fix_limit) { in mlx5e_ipsec_handle_limits()
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| /linux/include/linux/clk/ |
| H A D | renesas.h | 53 * various parameters used to configure a PLL. These limits ensure
193 bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits,
196 bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
200 static inline bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits, in rzv2h_cpg_get_pll_pars() argument
207 static inline bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, in rzv2h_cpg_get_pll_divs_pars() argument
|