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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltins.td87 let Spellings = ["__builtin_acos"];
88 let Attributes = [FunctionWithBuiltinPrefix, NoThrow,
90 let Prototype = "T(T)";
94 let Spellings = ["__builtin_acoshf128"];
95 let Attributes = [FunctionWithBuiltinPrefix, NoThrow,
97 let Prototype = "__float128(__float128)";
101 let Spellings = ["__builtin_asin"];
102 let Attributes = [FunctionWithBuiltinPrefix, NoThrow,
104 let Prototype = "T(T)";
108 let Spellings = ["__builtin_asinhf128"];
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H A DAttr.td25 let Content = [{
63 let Category = DocCatInternalOnly;
69 let Category = DocCatUndocumented;
70 let Content = "No documentation.";
445 let Arches = arches;
463 let OSes = ["Win32"];
466 let CustomCode = [{ Target.getTriple().hasDLLImportExport() }];
469 let CustomCode = [{ Target.getCXXABI().isItaniumFamily() }];
472 let CustomCode = [{ Target.getCXXABI().isMicrosoft() }];
475 let ObjectFormats = ["ELF"];
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrInfo.td16 let Inst{13-5} = 0b000000100;
17 let Inst{31-21} = 0b10001100100;
18 let hasNewValue = 1;
19 let opNewValue = 0;
20 let prefersSlot3 = 1;
27 let Inst{13-5} = 0b000000110;
28 let Inst{31-21} = 0b10000000100;
29 let prefersSlot3 = 1;
36 let Inst{13-5} = 0b000000101;
37 let Ins
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H A DHexagonDepInstrFormats.td13 let Inst{12-8} = Vu32{4-0};
15 let Inst{20-16} = Rt32{4-0};
17 let Inst{4-0} = Vdd32{4-0};
21 let Inst{11-5} = Ii{6-0};
23 let Inst{20-16} = Rs32{4-0};
25 let Inst{1-0} = Pd4{1-0};
29 let Inst{20-16} = Rss32{4-0};
31 let Inst{12-8} = Rt32{4-0};
33 let Inst{1-0} = Pd4{1-0};
37 let Ins
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H A DHexagonDepOperands.td16 def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperan…
17 def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDec…
19 def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOper…
20 def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0Imm…
22 def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands";…
23 def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsigned…
25 def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands";…
26 def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsigned…
28 def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands";…
29 def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsigned…
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td24 let Namespace = "Mips";
25 let DecoderNamespace = "MicroMips";
27 let OutOperandList = outs;
28 let InOperandList = ins;
30 let AsmString = asmstr;
31 let Pattern = pattern;
32 let Itinerary = itin;
34 let EncodingPredicates = [InMicroMips];
46 let Size = 2;
63 let Inst{15-10} = 0x01;
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H A DMipsMSAInstrFormats.td11 let EncodingPredicates = [HasStdEnc];
12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
26 let EncodingPredicates = [HasStdEnc];
27 let ASEPredicate = [HasMSA];
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
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H A DMicroMips32r6InstrFormats.td42 let Inst{15-10} = 0x33;
43 let Inst{9-0} = offset;
52 let Inst{15-10} = op;
53 let Inst{9-7} = rs;
54 let Inst{6-0} = offset;
62 let Inst{15-10} = 0x11;
63 let Inst{9-5} = rs;
64 let Inst{4-0} = op;
74 let Inst{31-26} = 0b011101;
75 let Inst{25-21} = rt;
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H A DMipsDSPInstrFormats.td12 let FilterClass = "DspMMRel";
14 let RowFields = ["BaseOpcode"];
16 let ColFields = ["Arch"];
18 let KeyCol = ["dsp"];
20 let ValueCols = [["dsp"], ["mmdsp"]];
48 let ASEPredicate = [HasDSP];
56 let ASEPredicate = [HasDSP];
61 let ASEPredicate = [HasDSP];
70 let Opcode = SPECIAL3_OPCODE.V;
72 let Inst{25-21} = rs;
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H A DMicroMipsDSPInstrFormats.td11 let ASEPredicate = [HasDSP];
12 let EncodingPredicates = [InMicroMips];
15 let DecoderNamespace = "MicroMips";
20 let ASEPredicate = [HasDSP];
21 let AdditionalPredicates = [InMicroMips];
29 let Inst{31-26} = 0b000000;
30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
33 let Inst{10-0} = op;
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H A DMipsInstrFormats.td41 let FilterClass = "MMRel";
43 let RowFields = ["BaseOpcode"];
45 let ColFields = ["Arch"];
47 let KeyCol = ["se"];
49 let ValueCols = [["se"], ["micromips"]];
55 let FilterClass = "StdMMR6Rel";
57 let RowFields = ["BaseOpcode"];
59 let ColFields = ["Arch"];
61 let KeyCol = ["se"];
63 let ValueCols = [["se"], ["micromipsr6"]];
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DGenericOpcodes.td19 let isPreISelOpcode = true;
32 let OutOperandList = baseInst.OutOperandList;
33 let InOperandList = baseInst.InOperandList;
34 let isCommutable = baseInst.isCommutable;
38 let hasSideEffects = true;
39 let mayRaiseFPException = true;
45 let OutOperandList = (outs type0:$dst);
46 let InOperandList = (ins type1:$src);
47 let hasSideEffects = false;
53 let OutOperandList = (outs type0:$dst);
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td12 let Namespace = "PPC" in {
31 let Namespace = "PPC";
38 let HWEncoding{4-0} = num;
43 let HWEncoding = SubReg.HWEncoding;
44 let SubRegs = [SubReg];
45 let SubRegIndices = [sub_32];
49 let HWEncoding{4-0} = Enc;
50 let SubRegs = subregs;
51 let SubRegIndices = [sub_32, sub_32_hi_phony];
52 let CoveredBySubRegs = 1;
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H A DPPCInstrFormats.td17 let Size = 4;
21 let Namespace = "PPC";
22 let Inst{0-5} = opcode;
23 let OutOperandList = OOL;
24 let InOperandList = IOL;
25 let AsmString = asmstr;
26 let Itinerary = itin;
35 let TSFlags{0} = PPC970_First;
36 let TSFlags{1} = PPC970_Single;
37 let TSFlag
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td26 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
27 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
28 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
29 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
30 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
31 let ReleaseAtCycles = [17]; }
32 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
33 let ReleaseAtCycles = [18]; }
34 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
35 let ReleaseAtCycle
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H A DARMInstrFormats.td144 let PrintMethod = "printCPSIMod";
148 let Name = "ProcIFlags";
149 let ParserMethod = "parseProcIFlagsOperand";
152 let PrintMethod = "printCPSIFlag";
153 let ParserMatchClass = ProcIFlagsOperand;
159 let Name = "CondCode";
160 let DefaultMethod = "defaultCondCodeOp";
161 let IsOptional = true;
165 let PrintMethod = "printPredicateOperand";
166 let ParserMatchClass = CondCodeOperand;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedKryoDetails.td16 let Latency = 3; let NumMicroOps = 2;
23 let Latency = 3; let NumMicroOps = 2;
30 let Latency = 4; let NumMicroOps = 3;
36 let Latency = 4; let NumMicroOps = 4;
42 let Latency = 3; let NumMicroOps = 4;
48 let Latency = 3; let NumMicroOps = 2;
54 let Latency = 3; let NumMicroOps = 2;
60 let Latency = 3; let NumMicroOps = 2;
66 let Latency = 3; let NumMicroOps = 2;
72 let Latency = 3; let NumMicroOps = 2;
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H A DAArch64SchedA57WriteRes.td29 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
30 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
31 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
32 def A57Write_5cyc_1V_FP_Forward : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
33 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
34 def A57Write_5cyc_1W_Mul_Forward : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
35 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
36 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
37 let ReleaseAtCycles = [17]; }
38 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latenc
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/freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/
H A DOMP.td20 let name = "OpenMP";
21 let cppNamespace = "omp"; // final namespace will be llvm::omp
22 let directivePrefix = "OMPD_";
23 let clausePrefix = "OMPC_";
24 let makeEnumAvailableInNamespace = true;
25 let enableBitmaskEnumInNamespace = true;
26 let clauseEnumSetClass = "OmpClauseSet";
27 let flangClauseBaseClass = "OmpClause";
36 let clangClass = "OMPAcquireClause";
39 let clangClass = "OMPAcqRelClause";
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrOperands.td16 let Name = "Mem";
18 let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in {
19 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
20 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
21 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
22 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
23 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
24 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
25 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
26 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td159 let TSFlags{0} = SALU;
160 let TSFlags{1} = VALU;
162 let TSFlags{2} = SOP1;
163 let TSFlags{3} = SOP2;
164 let TSFlags{4} = SOPC;
165 let TSFlags{5} = SOPK;
166 let TSFlags{6} = SOPP;
168 let TSFlags{7} = VOP1;
169 let TSFlags{8} = VOP2;
170 let TSFlags{9} = VOPC;
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H A DR600InstrFormats.td19 let SubtargetPredicate = isR600toCayman;
42 let SubtargetPredicate = isR600toCayman;
43 let Namespace = "R600";
44 let OutOperandList = outs;
45 let InOperandList = ins;
46 let AsmString = asm;
47 let Pattern = pattern;
48 let Itinerary = itin;
51 let isCodeGenOnly = 1;
53 let TSFlags{4} = Trig;
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H A DVOPInstructions.td9 // dummies for outer let
50 let mayLoad = 0;
51 let mayStore = 0;
52 let hasSideEffects = 0;
53 let UseNamedOperandTable = 1;
54 let VALU = 1;
55 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
63 let isPseudo = 1;
64 let isCodeGenOnly = 1;
65 let UseNamedOperandTable = 1;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td63 let Inst{31} = 1;
64 let Inst{30} = 1;
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
68 let Inst{11-7} = rd;
69 let Inst{6-0} = OPC_OP_V.Value;
71 let Defs = [VTYPE, VL];
80 let Inst{31} = 0;
81 let Inst{30-20} = vtypei;
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/freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/OpenACC/
H A DACC.td20 let name = "OpenACC";
21 let cppNamespace = "acc"; // final namespace will be llvm::acc
22 let directivePrefix = "ACCD_";
23 let clausePrefix = "ACCC_";
24 let makeEnumAvailableInNamespace = true;
25 let enableBitmaskEnumInNamespace = true;
26 let clauseEnumSetClass = "AccClauseSet";
27 let flangClauseBaseClass = "AccClause";
36 let flangClass = "ScalarIntExpr";
37 let isValueOptional = true;
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