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/linux/arch/sh/kernel/
H A Drelocate_kernel.S47 ldc r8, sr
62 ldc r8, sr
94 ldc r8, sr
108 ldc r8, sr
123 ldc r8, sr
126 ldc.l @r15+, spc
128 ldc.l @r15+, sr
129 ldc.l @r15+, ssr
130 ldc.l @r15+, gbr
H A Ddisassemble.c89 {"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}},
90 {"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}},
91 {"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}},
92 {"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}},
93 {"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}},
94 {"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}},
95 {"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}},
96 {"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}},
97 {"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}},
98 {"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}},
[all …]
H A Dirq_32.c18 "ldc %0, sr\n\t" in arch_local_irq_restore()
31 "ldc %0, sr\n\t" in arch_local_irq_restore()
H A Dhead_32.S60 ldc r0, sr
64 ldc r0, r6_bank
86 ldc r0, r7_bank ! ... and initial thread_info
/linux/arch/sh/kernel/cpu/shmobile/
H A Dsleep.S38 ldc r5, vbr
222 ldc r8, sr
254 ldc k1, vbr
258 ldc k0, sr
265 ldc r0, spc
269 ldc r0, vbr
273 ldc r0, ssr
384 ldc r8, sr
/linux/arch/sh/kernel/cpu/sh3/
H A Dswsusp.S67 ldc k3, ssr
98 ldc r1, ssr ! save sr in ssr
100 ldc r1, spc ! setup pc value for resuming
123 ldc r1, sr ! restore old sr
H A Dentry.S34 * ldc k1, ssr ! delay slot
199 ldc k3, ssr
229 ldc r9, sr
239 ldc.l @r15+, spc
242 ldc.l @r15+, gbr
271 ldc k2, ssr
322 ldc k0, spc ! PC = saved r0 + r15 - 2
422 ldc r8, sr
/linux/arch/sh/include/asm/
H A Dswitch_to_32.h27 "ldc.l @r2+, rs\n\t" \
28 "ldc.l @r2+, re\n\t" \
29 "ldc.l @r2+, mod\n\t" \
122 "ldc.l @r15+, gbr\n\t" \
H A Dbl_bit_32.h13 "ldc %0, sr\n\t" in set_bl_bit()
27 "ldc %0, sr\n\t" in clear_bl_bit()
H A Dentry-macros.S7 ldc r0, sr
20 ldc r10, sr
H A Dprocessor_32.h142 "ldc %0, sr" in disable_fpu()
154 "ldc %0, sr" in enable_fpu()
H A Dtraps_32.h36 "ldc %0, sr\n\t" in trigger_address_error()
/linux/arch/arm/probes/kprobes/
H A Dtest-arm.c1191 TEST_COPROCESSOR("ldc"two" p0, cr0, [r13, #4]") \ in kprobe_arm_test_cases()
1192 TEST_COPROCESSOR("ldc"two" p0, cr0, [r13, #-4]") \ in kprobe_arm_test_cases()
1193 TEST_COPROCESSOR("ldc"two" p0, cr0, [r13, #4]!") \ in kprobe_arm_test_cases()
1194 TEST_COPROCESSOR("ldc"two" p0, cr0, [r13, #-4]!") \ in kprobe_arm_test_cases()
1195 TEST_COPROCESSOR("ldc"two" p0, cr0, [r13], #4") \ in kprobe_arm_test_cases()
1196 TEST_COPROCESSOR("ldc"two" p0, cr0, [r13], #-4") \ in kprobe_arm_test_cases()
1197 TEST_COPROCESSOR("ldc"two" p0, cr0, [r13], {1}") \ in kprobe_arm_test_cases()
1198 TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13, #4]") \ in kprobe_arm_test_cases()
1199 TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13, #-4]") \ in kprobe_arm_test_cases()
1200 TEST_COPROCESSOR("ldc"two"l p0, cr0, [r13, #4]!") \ in kprobe_arm_test_cases()
[all …]
/linux/drivers/tty/
H A Dvcc.c16 #include <asm/ldc.h>
320 /* Read as long as LDC has incoming data. */ in vcc_ldc_read()
426 * vcc_event() - LDC event processing engine
428 * @event: LDC event
430 * Handles LDC events for VCC
457 pr_err("VCC: unexpected LDC event(%d)\n", event); in vcc_event()
555 * domain. Sets up VIO/LDC link between the guest & control
678 * VIO/LDC link between guest and primary domains.
748 pr_err("VCC: open: LDC channel not configured\n"); in vcc_open()
/linux/arch/sh/kernel/cpu/irq/
H A Dimask.c37 "ldc %2, r6_bank\n\t" in set_interrupt_registers()
47 "ldc %0, sr\n" in set_interrupt_registers()
/linux/arch/sh/kernel/cpu/sh2a/
H A Dentry.S156 ldc.l @r0+,gbr
196 ldc r0,sr ! all interrupt block (same BL = 1)
203 ldc.l @r0+,gbr
/linux/arch/sh/boards/mach-hp6xx/
H A Dpm.c73 asm volatile("ldc %0, vbr" : : "r" (vbr_new)); in pm_enter()
80 asm volatile("ldc %0, vbr" : : "r" (vbr_old)); in pm_enter()
/linux/arch/sh/kernel/cpu/sh2/
H A Dentry.S210 ldc.l @r0+,gbr
267 ldc r0,sr ! all interrupt block (same BL = 1)
274 ldc.l @r0+,gbr
/linux/arch/sparc/prom/
H A Dp1275.c19 #include <asm/ldc.h>
/linux/Documentation/arch/sh/
H A Dregister-banks.rst18 r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
/linux/arch/sh/kernel/cpu/
H A Dinit.c238 "ldc\t%0, sr\n\t" in release_dsp()
255 "ldc\t%0, sr\n\t" in dsp_init()
/linux/arch/arm/mm/
H A Dabort-lv4t.S49 /* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
50 /* d */ b do_DataAbort @ ldc rd, [rn, #m]
/linux/arch/sparc/include/asm/
H A Dhypervisor.h77 #define HV_ECHANNEL 16 /* Invalid LDC channel */
2852 * Configure transmit queue for the LDC endpoint specified by the
2867 * specified even in the event that the LDC is down (peer endpoint has no
2890 * Return the configuration info for the transmit queue of LDC endpoint
2911 * the transmit queue of the LDC endpoint defined by the given channel ID.
2924 * Update the tail pointer for the transmit queue associated with the LDC
2946 * Configure receive queue for the LDC endpoint specified by the
2955 * If a valid receive queue is specified for a local endpoint the LDC is
2982 * Return the configuration info for the receive queue of LDC endpoint
3003 * the receive queue of the LDC endpoint defined by the given channel ID.
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-trimslice.dts143 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
236 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
/linux/arch/sh/boot/compressed/
H A Dhead_32.S17 ldc r1, sr

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