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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td11 // latency and microOps. The naming conventions is to use a prefix, one field
12 // for latency, and one or more microOp count/type designators.
14 // Latency: #cyc
17 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
26 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
27 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
28 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
29 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
30 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
32 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency
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H A DARMScheduleM7.td36 // ReadAdvance<0> (the default) for their source operands and Latency = 1.
54 // Subtarget-specific SchedWrite types with map ProcResources and set latency.
56 def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
59 let Latency = 1 in {
66 def : WriteRes<WriteCMP, [M7UnitALU]> { let Latency = 1; }
67 def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
68 def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
71 let Latency = 2 in {
79 let Latency = 2 in {
82 def : WriteRes<WriteMAC64Lo, [M7UnitMAC]> { let Latency = 2; }
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA57WriteRes.td11 // latency and microOps. The naming conventions is to use a prefix, one field
12 // for latency, and one or more microOp count/type designators.
14 // Latency: #cyc
21 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
29 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
30 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
31 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
32 def A57Write_5cyc_1V_FP_Forward : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
33 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
34 def A57Write_5cyc_1W_Mul_Forward : SchedWriteRes<[A57UnitW]> { let Latency
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H A DAArch64SchedKryoDetails.td9 // This file defines the uop and latency details for the machine model for the
16 let Latency = 3; let NumMicroOps = 2;
23 let Latency = 3; let NumMicroOps = 2;
30 let Latency = 4; let NumMicroOps = 3;
36 let Latency = 4; let NumMicroOps = 4;
42 let Latency = 3; let NumMicroOps = 4;
48 let Latency = 3; let NumMicroOps = 2;
54 let Latency = 3; let NumMicroOps = 2;
60 let Latency = 3; let NumMicroOps = 2;
66 let Latency = 3; let NumMicroOps = 2;
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H A DAArch64SchedKryo.td16 // uops. Now, the latency spreadsheet has information based on fragmented uops,
22 let LoadLatency = 4; // Optimistic load latency
63 // Map the target-defined scheduler read/write resources and latency for
66 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
67 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
69 { let Latency = 2; let NumMicroOps = 2; }
71 { let Latency = 2; let NumMicroOps = 2; }
73 { let Latency = 2; let NumMicroOps = 2; }
74 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
76 { let Latency
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H A DAArch64SchedAmpere1.td22 let LoadLatency = 4; // Optimistic load latency
58 let Latency = 1;
63 let Latency = 1;
68 let Latency = 1;
73 let Latency = 1;
78 let Latency = 1;
83 let Latency = 1;
88 let Latency = 1;
93 let Latency = 2;
98 let Latency = 2;
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H A DAArch64SchedA64FX.td16 let LoadLatency = 5; // Optimistic load latency.
95 let Latency = 1;
99 let Latency = 2;
103 let Latency = 4;
107 let Latency = 6;
111 let Latency = 8;
115 let Latency = 9;
119 let Latency = 3;
123 let Latency = 5;
127 let Latency
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H A DAArch64SchedAmpere1B.td22 let LoadLatency = 3; // Optimistic load latency
53 let Latency = 1;
58 let Latency = 1;
63 let Latency = 1;
68 let Latency = 1;
73 let Latency = 1;
78 let Latency = 1;
83 let Latency = 1;
88 let Latency = 1;
93 let Latency = 1;
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H A DAArch64SchedExynosM4.td136 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
142 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
143 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
144 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
147 M4UnitC]> { let Latency = 2;
151 M4UnitC]> { let Latency = 3;
154 M4UnitC]> { let Latency = 2;
156 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td19 // Load latency is 4 or 5 cycles depending on the load. This latency assumes
20 // that we have a cache hit. For a cache miss the load latency will be more.
21 // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
139 let Latency = 1;
146 let Latency = 1;
153 let Latency = 1;
159 let Latency = 1;
164 let Latency = 1;
170 let Latency
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H A DPPCScheduleP10.td70 let NumMicroOps = 0, Latency = 1 in {
86 let Latency = 7;
91 let Latency = 22;
96 let Latency = 24;
101 let Latency = 26;
106 let Latency = 27;
111 let Latency = 36;
116 let Latency = 2;
121 let Latency = 7;
127 let Latency
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H A DPPCScheduleE5500.td52 [5, 2, 2], // Latency = 1
57 [5, 2, 2], // Latency = 1
62 [5, 2, 2, 2], // Latency = 1
68 [6, 2, 2], // Latency = 1 or 2
74 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
80 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
85 [11], // Latency = 7, Repeat rate = 1
89 [11, 2, 2], // Latency = 7, Repeat rate = 7
94 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
100 [8, 2, 2], // Latency = 4, Repeat rate = 1
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H A DPPCScheduleE500mc.td48 [4, 1, 1], // Latency = 1
53 [4, 1, 1], // Latency = 1
58 [4, 1, 1, 1], // Latency = 1
64 [5, 1, 1], // Latency = 1 or 2
70 [17, 1, 1], // Latency=4..35, Repeat= 4..35
75 [11], // Latency = 8
79 [11, 1, 1], // Latency = 8
83 [7, 1, 1], // Latency = 4, Repeat rate = 1
88 [7, 1, 1], // Latency = 4, Repeat rate = 1
93 [7, 1, 1], // Latency = 4, Repeat rate = 1
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H A DPPCScheduleE500.td43 [4, 1, 1], // Latency = 1
48 [4, 1, 1], // Latency = 1
53 [4, 1, 1, 1], // Latency = 1
59 [5, 1, 1], // Latency = 1 or 2
65 [17, 1, 1], // Latency=4..35, Repeat= 4..35
70 [7, 1, 1], // Latency = 4, Repeat rate = 1
75 [7, 1, 1], // Latency = 4, Repeat rate = 1
80 [7, 1, 1], // Latency = 4, Repeat rate = 1
85 [4, 1, 1], // Latency = 1
90 [4, 1, 1], // Latency = 1
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cpu-opp.dtsi9 clock-latency-ns = <100000>;
15 clock-latency-ns = <100000>;
21 clock-latency-ns = <100000>;
27 clock-latency-ns = <100000>;
33 clock-latency-ns = <100000>;
39 clock-latency-ns = <100000>;
45 clock-latency-ns = <100000>;
52 clock-latency-ns = <100000>;
59 clock-latency-ns = <100000>;
66 clock-latency-ns = <100000>;
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H A Dtegra20-cpu-opp.dtsi9 clock-latency-ns = <400000>;
16 clock-latency-ns = <400000>;
23 clock-latency-ns = <400000>;
29 clock-latency-ns = <400000>;
35 clock-latency-ns = <400000>;
41 clock-latency-ns = <400000>;
48 clock-latency-ns = <400000>;
54 clock-latency-ns = <400000>;
60 clock-latency-ns = <400000>;
66 clock-latency-ns = <400000>;
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8996pro.dtsi26 clock-latency-ns = <200000>;
32 clock-latency-ns = <200000>;
38 clock-latency-ns = <200000>;
44 clock-latency-ns = <200000>;
50 clock-latency-ns = <200000>;
56 clock-latency-ns = <200000>;
62 clock-latency-ns = <200000>;
68 clock-latency-ns = <200000>;
74 clock-latency-ns = <200000>;
80 clock-latency-ns = <200000>;
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/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dqcom-nvmem-cpufreq.txt152 clock-latency-ns = <200000>;
158 clock-latency-ns = <200000>;
164 clock-latency-ns = <200000>;
170 clock-latency-ns = <200000>;
176 clock-latency-ns = <200000>;
182 clock-latency-ns = <200000>;
188 clock-latency-ns = <200000>;
194 clock-latency-ns = <200000>;
200 clock-latency-ns = <200000>;
206 clock-latency-ns = <200000>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedAlderlakeP.td21 // Latency for microcoded instructions or instructions without latency info.
111 let Latency = Lat;
117 // the latency (default = 5).
119 let Latency = !add(Lat, LoadLat);
138 let Latency = 11;
152 let Latency = 11;
214 let Latency = 3;
227 let Latency = 3;
254 let Latency = 7;
257 let Latency = 7;
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H A DX86SchedSapphireRapids.td21 // Latency for microcoded instructions or instructions without latency info.
104 let Latency = Lat;
110 // the latency (default = 5).
112 let Latency = !add(Lat, LoadLat);
131 let Latency = 11;
145 let Latency = 11;
221 let Latency = 3;
231 let Latency = 3;
250 let Latency = 7;
253 let Latency = 7;
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H A DX86SchedSkylakeClient.td36 // the store address, but since we don't model the latency of stores, we can
96 let Latency = Lat;
102 // the latency (default = 5).
104 let Latency = !add(Lat, LoadLat);
132 def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
134 let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency);
169 let Latency = 2;
212 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
219 // Branches don't produce values, so they have no latency, but they still
427 let Latency = 2;
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H A DX86SchedSkylakeServer.td36 // the store address, but since we don't model the latency of stores, we can
96 let Latency = Lat;
102 // the latency (default = 5).
104 let Latency = !add(Lat, LoadLat);
133 def SKXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
135 let Latency = !add(SKXWriteIMulH.Latency, SkylakeServerModel.LoadLatency);
170 let Latency = 2;
212 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
219 // Branches don't produce values, so they have no latency, but they still
428 let Latency = 2;
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Didle-states.yaml39 Idle state parameters (e.g. entry latency) are platform specific and need to
61 | latency |
63 | latency |
65 |<------- wakeup-latency ------->|
73 event conditions. The abort latency is assumed to be negligible
87 entry-latency: Worst case latency required to enter the idle state. The
88 exit-latency may be guaranteed only after entry-latency has passed.
93 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
95 to be entry-latency + exit-latency.
107 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
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/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Didle-states.yaml44 Idle state parameters (e.g. entry latency) are platform specific and need to
81 | latency |
83 | latency |
85 |<------- wakeup-latency ------->|
93 event conditions. The abort latency is assumed to be negligible
107 entry-latency: Worst case latency required to enter the idle state. The
108 exit-latency may be guaranteed only after entry-latency has passed.
113 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
115 to be entry-latency + exit-latency.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
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/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A Dmemory.json25 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
35 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency…
41 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
51 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency…
57 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
67 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency…
73 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
83 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency…
89 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
99 …ds when the latency from first dispatch to completion is greater than 4 cycles. Reported latency …
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