| /linux/include/uapi/linux/ |
| H A D | atmlec.h | 33 l_narp_req, /* LANE2 mandates the use of this */
54 unsigned int lane_version; /* LANE2: 1 for LANEv1, 2 for LANEv2 */
61 int sizeoftlvs; /* LANE2: if != 0, tlvs follow */
71 unsigned int targetless_le_arp; /* LANE2 */
72 unsigned int no_source_le_narp; /* LANE2 */
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-rockchip-usbdp.yaml | 64 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
67 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
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| H A D | qcom,msm8996-qmp-pcie-phy.yaml | 89 - lane2
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| H A D | fsl,imx8qm-hsio.yaml | 55 | | Lane0| Lane1| Lane2|
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| /linux/net/atm/ |
| H A D | lec.h | 36 * Operations that LANE2 capable device can do. Two first functions
140 u8 *tlvs; /* LANE2: TLVs are new */
142 int lane_version; /* LANE2 */
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| H A D | lec_arpc.h | 46 * LANE2: Each MAC address can have TLVs
55 * LANE2: Template tlv struct for accessing
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| H A D | lec.c | 71 /* LANE2 functions */
375 case l_narp_req: /* LANE2: see 7.1.35 in the lane2 spec */ in lec_atm_send()
390 if (mesg->sizeoftlvs != 0) { /* LANE2 3.1.5 */ in lec_atm_send()
391 pr_debug("LANE2 3.1.5, got tlvs, size %d\n", in lec_atm_send()
412 /* LANE2 */ in lec_atm_send()
505 * LANE2: new argument struct sk_buff *data contains
506 * the LE_ARP based TLVs introduced in the LANE2 spec
760 priv->itfnum = i; /* LANE2 addition */ in lecd_attach()
1077 * LANE2: 3.1.3, LE_RESOLVE.request
1123 * LANE2: 3.1.4, LE_ASSOCIATE.request
[all …]
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| H A D | mpc.c | 365 * We fill in the pointer above when we see a LANE2 lec initializing
366 * See LANE2 spec 3.1.5
827 if (mpc->dev) { /* check if the lec is LANE2 capable */ in atm_mpoa_mpoad_attach()
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| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8qm-hsio.c | 370 * Except the phy_off, the bit-offset of lane2 is same to lane0. in imx_hsio_power_on()
371 * Merge the lane0 and lane2 bit-operations together. in imx_hsio_power_on()
432 * Except the phy_off, the bit-offset of lane2 is same in imx_hsio_power_off()
433 * to lane0. Merge the lane0 and lane2 bit-operations in imx_hsio_power_off()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | mediatek-pcie-gen3.yaml | 91 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
299 - const: phy-lane2
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| /linux/arch/arm64/boot/dts/airoha/ |
| H A D | en7581.dtsi | 223 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
266 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
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| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-comphy.c | 32 /* Comphy lane2 indirect access register offset */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
475 /* SATA must be in Lane2 */ in mvebu_a3700_comphy_set_phy_selector()
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| /linux/drivers/gpu/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 244 uint8_t lane2:2; /* Mapping for lane 2 */ member
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 189 "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-dphy-rx0.c | 214 /* HS RX Control of lane2 */ in rk_dphy_enable()
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| /linux/drivers/phy/ti/ |
| H A D | phy-j721e-wiz.c | 66 LANE2 = 2, enumerator
1285 case LANE2: in wiz_phy_reset_deassert()
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| /linux/drivers/gpu/drm/msm/registers/display/ |
| H A D | dsi.xml | 100 <bitfield name="LANE2" pos="6" type="boolean"/>
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| /linux/lib/zstd/compress/ |
| H A D | zstd_compress.c | 6917 * we use _mm256_permute4x64_epi64(..., 0xE8) to move lane2 into lane1,
6970 * Explanation of 0xE8 = 11101000b => [lane0, lane2, lane2, lane3]. in convertSequences_noRepcodes()
6971 * So the lower 128 bits become [lane0, lane2] => combining seq0 and seq1. in convertSequences_noRepcodes()
7005 * Lane2 = seq1's 8 bytes in convertSequences_noRepcodes()
7009 /* Permute 64-bit lanes => move Lane2 down into Lane1. */ in convertSequences_noRepcodes()
7013 * The upper 16 bytes are [Lane2, Lane3] = [seq1, 0], but we won't use them. in convertSequences_noRepcodes()
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| /linux/drivers/pci/controller/ |
| H A D | pcie-mediatek-gen3.c | 1357 .id[2] = "phy-lane2",
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 4111 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 4604 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
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