Searched full:lane2 (Results 1 – 11 of 11) sorted by relevance
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-rockchip-usbdp.yaml | 64 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
67 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
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| H A D | qcom,msm8996-qmp-pcie-phy.yaml | 89 - lane2
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| H A D | fsl,imx8qm-hsio.yaml | 55 | | Lane0| Lane1| Lane2|
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| /linux/arch/arm64/boot/dts/airoha/ |
| H A D | en7581.dtsi | 223 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
266 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
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| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-comphy.c | 32 /* Comphy lane2 indirect access register offset */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
475 /* SATA must be in Lane2 */ in mvebu_a3700_comphy_set_phy_selector()
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 189 "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-dphy-rx0.c | 214 /* HS RX Control of lane2 */ in rk_dphy_enable()
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| /linux/lib/zstd/compress/ |
| H A D | zstd_compress.c | 6917 * we use _mm256_permute4x64_epi64(..., 0xE8) to move lane2 into lane1,
6970 * Explanation of 0xE8 = 11101000b => [lane0, lane2, lane2, lane3]. in convertSequences_noRepcodes()
6971 * So the lower 128 bits become [lane0, lane2] => combining seq0 and seq1. in convertSequences_noRepcodes()
7005 * Lane2 = seq1's 8 bytes in convertSequences_noRepcodes()
7009 /* Permute 64-bit lanes => move Lane2 down into Lane1. */ in convertSequences_noRepcodes()
7013 * The upper 16 bytes are [Lane2, Lane3] = [seq1, 0], but we won't use them. in convertSequences_noRepcodes()
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| /linux/drivers/pci/controller/ |
| H A D | pcie-mediatek-gen3.c | 1420 .id[2] = "phy-lane2",
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 4111 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 4604 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
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