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Searched full:lane2 (Results 1 – 15 of 15) sorted by relevance

/linux/include/uapi/linux/
H A Datmlec.h33 l_narp_req, /* LANE2 mandates the use of this */
54 unsigned int lane_version; /* LANE2: 1 for LANEv1, 2 for LANEv2 */
61 int sizeoftlvs; /* LANE2: if != 0, tlvs follow */
71 unsigned int targetless_le_arp; /* LANE2 */
72 unsigned int no_source_le_narp; /* LANE2 */
/linux/net/atm/
H A Dlec.h36 * Operations that LANE2 capable device can do. Two first functions
140 u8 *tlvs; /* LANE2: TLVs are new */
142 int lane_version; /* LANE2 */
H A Dlec_arpc.h46 * LANE2: Each MAC address can have TLVs
55 * LANE2: Template tlv struct for accessing
H A Dlec.c71 /* LANE2 functions */
373 case l_narp_req: /* LANE2: see 7.1.35 in the lane2 spec */ in lec_atm_send()
388 if (mesg->sizeoftlvs != 0) { /* LANE2 3.1.5 */ in lec_atm_send()
389 pr_debug("LANE2 3.1.5, got tlvs, size %d\n", in lec_atm_send()
410 /* LANE2 */ in lec_atm_send()
503 * LANE2: new argument struct sk_buff *data contains
504 * the LE_ARP based TLVs introduced in the LANE2 spec
754 priv->itfnum = i; /* LANE2 addition */ in lecd_attach()
1068 * LANE2: 3.1.3, LE_RESOLVE.request
1114 * LANE2: 3.1.4, LE_ASSOCIATE.request
[all …]
H A Dmpc.c365 * We fill in the pointer above when we see a LANE2 lec initializing
366 * See LANE2 spec 3.1.5
827 if (mpc->dev) { /* check if the lec is LANE2 capable */ in atm_mpoa_mpoad_attach()
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c370 * Except the phy_off, the bit-offset of lane2 is same to lane0. in imx_hsio_power_on()
371 * Merge the lane0 and lane2 bit-operations together. in imx_hsio_power_on()
432 * Except the phy_off, the bit-offset of lane2 is same in imx_hsio_power_off()
433 * to lane0. Merge the lane0 and lane2 bit-operations in imx_hsio_power_off()
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,msm8996-qmp-pcie-phy.yaml89 - lane2
H A Dfsl,imx8qm-hsio.yaml55 | | Lane0| Lane1| Lane2|
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c32 /* Comphy lane2 indirect access register offset */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
475 /* SATA must be in Lane2 */ in mvebu_a3700_comphy_set_phy_selector()
/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h244 uint8_t lane2:2; /* Mapping for lane 2 */ member
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c214 /* HS RX Control of lane2 */ in rk_dphy_enable()
/linux/drivers/gpu/drm/msm/registers/display/
H A Ddsi.xml100 <bitfield name="LANE2" pos="6" type="boolean"/>
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi739 reset-names = "lane2";
/linux/drivers/gpu/drm/radeon/
H A Datombios.h4112 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h4604 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …