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/linux/drivers/phy/tegra/
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
308 usb2->base.index = index; in tegra186_usb2_lane_probe()
309 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
[all …]
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
297 return -ENODEV; in tegra124_usb3_save_context()
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H A Dxusb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
19 /* legacy entry points for backwards-compatibility */
55 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dparade,ps8622.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 - parade,ps8622
16 - parade,ps8625
21 lane-count:
26 use-external-pwm:
30 reset-gpios:
34 sleep-gpios:
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
45 * IOSF-SB port.
48 * houses a common lane part which contains the PLL and other common
49 * logic. CH0 common lane also contains the IOSF-SB logic for the
59 * each spline is made up of one Physical Access Coding Sub-Layer
64 * Additionally the PHY also contains an AUX lane with AUX blocks
70 * Generally on VLV/CHV the common lane corresponds to the pipe and
103 * ---------------------------------
106 * |---------------|---------------| Display PHY
108 * |-------|-------|-------|-------|
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H A Dintel_dp_link_training.c2 * Copyright © 2008-2015 Intel Corporation
35 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \
36 (_intel_dp)->attached_connector->base.name, \
37 dp_to_dig_port(_intel_dp)->base.base.base.id, \
38 dp_to_dig_port(_intel_dp)->base.base.name, \
42 drm_dbg_kms(to_intel_display(_intel_dp)->drm, \
47 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \
48 drm_err(to_intel_display(_intel_dp)->drm, \
57 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); in intel_dp_reset_lttpr_common_caps()
62 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - in intel_dp_reset_lttpr_count()
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/linux/drivers/gpu/drm/bridge/
H A Dcros-ec-anx7688.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CrOS EC ANX7688 HDMI->DP bridge driver
58 if (!anx->filter) in cros_ec_anx7688_bridge_mode_fixup()
61 /* Read both regs 0x85 (bandwidth) and 0x86 (lane count). */ in cros_ec_anx7688_bridge_mode_fixup()
62 ret = regmap_bulk_read(anx->regmap, ANX7688_DP_BANDWIDTH_REG, regs, 2); in cros_ec_anx7688_bridge_mode_fixup()
64 DRM_ERROR("Failed to read bandwidth/lane count\n"); in cros_ec_anx7688_bridge_mode_fixup()
72 DRM_ERROR("Invalid bandwidth/lane count (%02x/%d)\n", dpbw, in cros_ec_anx7688_bridge_mode_fixup()
81 requiredbw = mode->clock * 8 * 3; in cros_ec_anx7688_bridge_mode_fixup()
87 DRM_ERROR("Bandwidth/lane count are 0, not rejecting modes\n"); in cros_ec_anx7688_bridge_mode_fixup()
100 struct device *dev = &client->dev; in cros_ec_anx7688_bridge_probe()
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/linux/drivers/net/ethernet/sfc/falcon/
H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
69 /* Lane power-down */
79 /* Bit position of value for lane 0 (or 2) */
81 /* Bit position of value for lane 1 (or 3) */
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/linux/Documentation/ABI/testing/
H A Dsysfs-devices-platform-kunpeng_hccs9 contains read-only attributes exposing some summarization
19 lane (bool).
20 crc_err_cnt: (RO) total CRC err count for all ports on this
32 contains read-only attributes exposing some summarization
43 lane (bool).
44 crc_err_cnt: (RO) total CRC err count for all ports on this
60 contains read-only attributes exposing information about
63 HCCS port belongs. For example, X ranges from to 'n - 1' if the
73 type: (RO) port type (string), e.g. HCCS-v1 -> H32
74 lane_mode: (RO) the lane mode of this port (string), e.g. x8
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/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
69 * is_link_rate_valid() - validates the link rate
83 * dp_link_is_lane_count_valid() - validates the lane count
84 * @lane_count: lane count requested by the sink
86 * Returns true if the requested lane count is supported.
H A Ddp_link.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
55 if (link->revision < 0x11) in dp_aux_link_power_up()
82 if (link->revision < 0x11) in dp_aux_link_power_down()
106 if (drm_dp_dpcd_readb(link->aux, addr, &data) < 0) { in dp_link_get_period()
108 ret = -EINVAL; in dp_link_get_period()
112 /* Period - Bits 3:0 */ in dp_link_get_period()
116 ret = -EINVAL; in dp_link_get_period()
128 struct dp_link_test_audio *req = &link->dp_link.test_audio; in dp_link_parse_audio_channel_period()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c42 link->ctx->logger
52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
55 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
58 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1); in dp_fixed_vs_pe_read_lane_adjust()
60 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
63 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1); in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
[all …]
H A Dlink_dp_training_8b_10b.c36 link->ctx->logger
46 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_cr_training_aux_rd_interval()
72 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
100 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set; in decide_8b_10b_training_settings()
101 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set; in decide_8b_10b_training_settings()
102 lt_settings->link_settings.link_rate = link_setting->link_rate; in decide_8b_10b_training_settings()
103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
107 * path_mode->display_path) ? in decide_8b_10b_training_settings()
111 lt_settings->link_settings.link_spread = link->dp_ss_off ? in decide_8b_10b_training_settings()
113 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting); in decide_8b_10b_training_settings()
[all …]
H A Dlink_dp_irq_handler.c42 link->ctx->logger
52 uint32_t lane; in dp_parse_link_loss_status() local
59 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status()
62 /*1. Check that Link Status changed, before re-training.*/ in dp_parse_link_loss_status()
64 /*parse lane status*/ in dp_parse_link_loss_status()
65 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status()
70 &hpd_irq_dpcd_data->bytes.lane01_status.raw, in dp_parse_link_loss_status()
71 lane); in dp_parse_link_loss_status()
87 if (link_dp_get_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING && in dp_parse_link_loss_status()
88 (!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b || in dp_parse_link_loss_status()
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/linux/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
34 * lane 0, used for the transmissions on main link.
44 * to be used by particular lanes. One value per lane.
45 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
55 * used by particular lanes. One value per lane.
64 * Flag indicating, whether or not to enable spread-spectrum clocking.
81 * Flag indicating, whether or not reconfigure lane count to
91 * and pre-emphasis to requested values. Only lanes specified
/linux/drivers/edac/
H A Dthunderx_edac.c8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
50 while (descr->type && descr->mask && descr->descr) { in decode_register()
51 if (reg & descr->mask) { in decode_register()
53 descr->type == ERR_CORRECTED ? in decode_register()
55 descr->descr); in decode_register()
57 size -= ret; in decode_register()
65 return (data >> pos) & ((1 << width) - 1); in get_bits()
121 .descr = "Single-bit ECC error",
131 .descr = "Double-bit ECC error",
136 .descr = "Non-existent memory write",
[all …]
/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_misc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
35 if (dsaf_dev->sub_ctrl) in dsaf_write_sub()
36 dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val); in dsaf_write_sub()
38 dsaf_write_reg(dsaf_dev->sc_base, reg, val); in dsaf_write_sub()
46 if (dsaf_dev->sub_ctrl) { in dsaf_read_sub()
47 err = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg, &ret); in dsaf_read_sub()
49 dev_err(dsaf_dev->dev, "dsaf_read_syscon error %d!\n", in dsaf_read_sub()
52 ret = dsaf_read_reg(dsaf_dev->sc_base, reg); in dsaf_read_sub()
72 argv4.package.count = 3; in hns_dsaf_acpi_ledctrl_by_port()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
72 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
74 if (!dp->force_hpd) in analogix_dp_detect_hpd()
75 return -ETIMEDOUT; in analogix_dp_detect_hpd()
82 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
87 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
88 return -EINVAL; in analogix_dp_detect_hpd()
91 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
101 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
103 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
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/linux/drivers/thunderbolt/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0
87 return single_open(file, __space ## _show, inode->i_private); \
108 size_t *count) in validate_and_copy_from_user() argument
113 if (!*count) in validate_and_copy_from_user()
114 return ERR_PTR(-EINVAL); in validate_and_copy_from_user()
116 if (!access_ok(user_buf, *count)) in validate_and_copy_from_user()
117 return ERR_PTR(-EFAULT); in validate_and_copy_from_user()
121 return ERR_PTR(-ENOMEM); in validate_and_copy_from_user()
123 nbytes = min_t(size_t, *count, PAGE_SIZE); in validate_and_copy_from_user()
126 return ERR_PTR(-EFAULT); in validate_and_copy_from_user()
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/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
H A Dlink_dp_cts.c39 link->ctx->logger
69 struct dc_state *state = link->dc->current_state; in dp_retrain_link_dp_test()
70 bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state); in dp_retrain_link_dp_test()
72 uint8_t count; in dp_retrain_link_dp_test() local
77 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); in dp_retrain_link_dp_test()
79 for (i = 0; i < count; i++) { in dp_retrain_link_dp_test()
81 pipes[i]->link_config.dp_link_settings = *link_setting; in dp_retrain_link_dp_test()
83 link->dc, in dp_retrain_link_dp_test()
88 if (link->dc->hwss.setup_hpo_hw_control) { in dp_retrain_link_dp_test()
91 link->dc->hwss.setup_hpo_hw_control(link->dc->hwseq, is_hpo_acquired); in dp_retrain_link_dp_test()
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/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c76 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
80 int lane) in dp_get_lane_status() argument
82 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
83 int s = (lane & 1) * 4; in dp_get_lane_status()
94 int lane; in drm_dp_channel_eq_ok() local
100 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
101 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
112 int lane; in drm_dp_clock_recovery_ok() local
115 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
116 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux/tools/testing/selftests/drivers/net/hw/
H A Ddevlink_port_split.py2 # SPDX-License-Identifier: GPL-2.0
12 # Test port split configuration using devlink-port lanes attribute.
15 # First, check that all the ports with 1 lane fail to split.
16 # Second, check that all the ports with more than 1 lane can be split
21 # Kselftest framework requirement - SKIP code is 4
57 cmd = "devlink -j port show"
81 cmd = "devlink -j port show %s" % port
99 cmd = "devlink -j port show %s" % port.name
115 cmd = "devlink port split %s count %s" % (port.bus_info, k)
176 print("TEST: %-60s [ OK ]" % msg)
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/linux/Documentation/devicetree/bindings/soundwire/
H A Dqcom,soundwire.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - qcom,soundwire-v1.3.0
20 - qcom,soundwire-v1.5.0
21 - qcom,soundwire-v1.5.1
22 - qcom,soundwire-v1.6.0
23 - qcom,soundwire-v1.7.0
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