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/freebsd/share/examples/ipfilter/l4check/
H A Dl4check.c98 addnat(l4cfg_t *l4) in addnat() argument
100 ipnat_t *ipn = &l4->l4_nat; in addnat()
113 delnat(l4cfg_t *l4) in delnat() argument
115 ipnat_t *ipn = &l4->l4_nat; in delnat()
128 connectl4(l4cfg_t *l4) in connectl4() argument
130 l4->l4_rw = 1; in connectl4()
131 l4->l4_rlen = 0; in connectl4()
132 l4->l4_wlen = plen; in connectl4()
133 if (!l4->l4_wlen) { in connectl4()
134 l4->l4_alive = 1; in connectl4()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/omap/
H A Dl4.txt1 L4 interconnect bindings
3 These bindings describe the OMAP SoCs L4 interconnect bus.
6 - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
7 Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
8 Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
9 Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
10 Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
11 Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
12 Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
13 Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
[all …]
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dqcom,smd-rpm-regulator.yaml27 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
36 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob
38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
44 For pm8909, s1, s2, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
47 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
50 For pm8937, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
53 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
57 For pm8950 and pm8953, s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6,
62 l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19,
66 l3, l4, l
[all...]
H A Dqcom,rpmh-regulator.yaml145 vdd-l4-l7-l8-supply: true
166 vdd-l4-l5-l6-supply: true
199 vdd-l4-l6-supply: true
211 vdd-l1-l4-l12-l15-supply: true
251 vdd-l3-l4-supply: true
266 vdd-l3-l4-l5-l18-supply: true
282 vdd-l4-supply: true
296 vdd-l1-l4-supply: true
315 vdd-l3-l4-l5-l7-l13-supply: true
338 vdd-l1-l4
[all...]
H A Dqcom,rpm-regulator.yaml19 For pm8058 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15,
23 For pm8901 l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3,
26 For pm8921 s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
31 For pm8018 s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
H A Dqcom,smd-rpm-regulator.txt249 s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
253 s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
258 s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5,
263 s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2, l3, l4,
268 s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5,
279 s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12,
/freebsd/lib/libc/i386/string/
H A Dstrncmp.S66 L2: jz L4 /* strings are equal */
88 jz L4
98 jz L4
108 jz L4
118 jz L4
128 jz L4
138 jz L4
148 jz L4
162 L4: xorl %eax,%eax label
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dti-clkctrl.txt20 "ti,clkctrl-l4-cfg"
21 "ti,clkctrl-l4-per"
22 "ti,clkctrl-l4-secure"
23 "ti,clkctrl-l4-wkup"
/freebsd/crypto/openssl/crypto/aes/asm/
H A Daes-sparcv9.pl66 $t0="%l4";
559 ldub [%i0+4],%l4
563 sll %l4,24,%l4
571 or %l5,%l4,%l4
575 or %l4,%l6,%o1
581 ldub [%i0+12],%l4
585 sll %l4,24,%l4
593 or %l5,%l4,%l4
595 or %l4,%l6,%o3
608 srl %o1,24,%l4
[all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A Dfrontend.json101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
185 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache…
186 …"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cach…
197 …rocessor's Instruction cache was reloaded from a memory location including L4 from local remote or…
198 …rocessor's Instruction cache was reloaded from a memory location including L4 from local remote or…
227 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the …
228 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the…
305 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
371 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
[all …]
H A Dmarked.json59 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
65 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Gr…
215 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
221 …"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked l…
239 … "The processor's data cache was reloaded from a memory location including L4 from local remote or…
245 …"BriefDescription": "Duration in cycles to reload from a memory location including L4 from local r…
299 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…
305 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group…
377 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
443 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
[all …]
H A Dmemory.json29 … "The processor's data cache was reloaded from a memory location including L4 from local remote or…
30 … "The processor's data cache was reloaded from a memory location including L4 from local remote or…
35 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…
36 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same N…
95 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
161 "BriefDescription": "Memory prefetch for this lpar. Includes L4",
167 …Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4",
/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini-wbd111.dts50 led-green-l4 {
51 label = "wbd111:green:L4";
56 led-red-l4 {
57 label = "wbd111:red:L4";
H A Dgemini-wbd222.dts49 led-green-l4 {
50 label = "wbd111:green:L4";
55 led-red-l4 {
56 label = "wbd111:red:L4";
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A Dextended.json107 "BriefDescription": "L1D On-Node L4 Sourced Writes",
125 "BriefDescription": "L1D On-Drawer L4 Sourced Writes",
143 "BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
215 "BriefDescription": "L1I On-Chip L4 Sourced Writes",
233 "BriefDescription": "L1I On-Drawer L4 Sourced Writes",
251 "BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
269 "BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A Dextended.json41 "BriefDescription": "L1D On-Book L4 Sourced Writes",
47 "BriefDescription": "L1I On-Book L4 Sourced Writes",
59 "BriefDescription": "L1D Off-Book L4 Sourced Writes",
65 "BriefDescription": "L1I Off-Book L4 Sourced Writes",
/freebsd/sys/contrib/ena-com/ena_defs/
H A Dena_eth_io_defs.h83 * 12:8 : l4_proto_idx - L4 protocol. This field need
91 * 17 : l4_csum_partial - L4 partial checksum. when
92 * set to 0, the ENA calculates the L4 checksum,
97 * the checksum field of the L4 is used instead. When
99 * must not include the tcp length field. L4 partial
118 * set to the sum of L4 header offset and L4 header
165 * 21:16 : l4_hdr_len_in_words - counts the L4 header
167 * that L4 header appears right after L3 header and
168 * L4 offset is based on l3_hdr_off+l3_hdr_len
237 * 14 : l4_csum_err - when set, either the L4
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_rfgain.c126 uint32_t L1, L2, L3, L4; in ar5212InvalidGainReadback() local
133 L4 = 107; in ar5212InvalidGainReadback()
136 L4 = 83; in ar5212InvalidGainReadback()
145 L4 = L3 + 50; in ar5212InvalidGainReadback()
149 gv->hiTrig = L4 - (gStep == 0x3f ? DYN_ADJ_UP_MARGIN : -5); in ar5212InvalidGainReadback()
153 return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4)); in ar5212InvalidGainReadback()
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dqcom,pm8008.yaml31 vdd-l3-l4-supply: true
93 - vdd-l3-l4-supply
125 vdd-l3-l4-supply = <&vreg_s1b_1p8>;
H A Dqcom-rpm.txt157 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15,
162 l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3,
166 s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
172 s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
/freebsd/crypto/openssl/crypto/whrlpool/
H A Dwp_block.c538 u64 L0, L1, L2, L3, L4, L5, L6, L7; in whirlpool_block()
575 L4 = C0(K, 4) ^ C1(K, 3) ^ C2(K, 2) ^ C3(K, 1) ^ in whirlpool_block()
588 K.q[4] = L4; in whirlpool_block()
601 L4 ^= C0(S, 4) ^ C1(S, 3) ^ C2(S, 2) ^ C3(S, 1) ^ in whirlpool_block()
614 S.q[4] = L4; in whirlpool_block()
623 L4 = C4(K, 0); in whirlpool_block()
632 L4 ^= C3(K, 1); in whirlpool_block()
640 L4 ^= C2(K, 2); in whirlpool_block()
648 L4 ^= C1(K, 3); in whirlpool_block()
656 L4 ^= C0(K, 4); in whirlpool_block()
[all …]
/freebsd/sys/arm/ti/clk/
H A Dti_clkctrl.c73 { "ti,clkctrl-l4-wkup", TI_CLKCTRL_L4_WKUP },
74 { "ti,clkctrl-l4-secure", TI_CLKCTRL_L4_SECURE },
75 { "ti,clkctrl-l4-per", TI_CLKCTRL_L4_PER },
76 { "ti,clkctrl-l4-cfg", TI_CLKCTRL_L4_CFG },
183 else if (strcmp(org_name, "l4-wkup-clkctrl@0") == 0) in ti_clkctrl_attach()
/freebsd/sys/dev/igc/
H A Digc_base.h69 #define IGC_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
70 #define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
71 #define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A Dmarked.json60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
190 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…
245 … "The processor's data cache was reloaded from a memory location including L4 from local remote or…
280 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
310 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache…
480 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
520 …"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked l…
525 "BriefDescription": "Memory prefetch for this thread. Includes L4"
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A Dextended.json107 "BriefDescription": "L1D On-Book L4 Sourced Writes",
113 "BriefDescription": "L1D Off-Book L4 Sourced Writes",
161 "BriefDescription": "L1I On-Book L4 Sourced Writes",
167 "BriefDescription": "L1I Off-Book L4 Sourced Writes",

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